ML7344J datasheet(47/151 Pages) ETC2

47 / 151 page

FEDL7344C/E/J-04

ML7344C/E/J

47/151

[RX]

L-field (Length) is read from [RX_PKT_LEN_H: B0 0x7D], [RX_PKT_LEN_L: B0 0x7E] registers.

ii) Reading RX data from FIFO. When reading from RX_FIFO, set FIFO_R_SEL([FIFO_SET: B0

0x78(0)])= 0b0. If FIFO_R_SEL=0b1 , TX_FIFO will be selected. Data usage value of RX_FIFO is

indicated by [RX_FIFO_LAST: B0 0x79] register.

NOTE:

1. If reading FIFO data is terminated before reading all data, STATE_CLR1 [STATE_CLR: B0 0x16(1)]

(RX FIFO pointer clear) must be issued. Otherwise If RX_FIFO is not cleared, the pointer controlling

FIFO data keeps the same status. Next RX data will not be processed in the FIFO properly.

For example, when RX_FIFO access error interrupt (INT[12] group2) is generated. This interrupt occurs

when RX_FIFO overrun (data received when no space in RX_FIFO) or underrun (reading empty

RX_FIFO).

2. If 1 packet data is kept in the RX_FIFO, next RX data will be overwritten.

IF TX/RX pack is larger than FIFO size, FIFO access can be controlled by FIFO-Full trigger or FIFO-Empty

trigger.

(1) TX_FIFO usage notification function

This function is to notice TX_FIFO usage to the MCU using interrupt (SINTN). If TX_FIFO usage

(un-transmitted data in TX_FIFO) exceed the Full level threshold set by [TXFIFO_THRH: B0 0x17] register,

interrupt will generate as FIFO-full interrupt (INT[5] group1). If TX_FIFO usage is smaller than Empty level

threshold set by [TXFIFO_THRL: B0 0x18] register, FIFO-Empty interrupt will generate as FIFO-Empty

interrout (INT[4] grou1). Interrupt signal (SINTN) can be output from GPIO* or EXT_CLK pin.

For output setting, please refer to [GPIO1_CTRL: B0 0x4E], [GPIO1_CTRL: B0 0x4F], [GPIO2_CTRL: B0

0x50], [GPIO3_CTRL: B0 0x51], [EXTCLK_CTRL: B0 0x52] registers for output setting.

Empty level

(Example 0x0F)

Full level

(Example 0x2E)

0x3F

Generate interrupt

when TX data

usage is smaller

than Empty level

[FIFO usage]

Time

Full level

Empty level

TX data amount

TX_FIFO usage

transition

0x0F

0x2E

SINTN signal

TX start timing by

FAST_TX trigger

Clear interrupt

0x00

Generate interrupt

when written Data

exceed Full level

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