TSB41AB2PAPG4 datasheet(44/55 Pages) TI1

44 / 55 page

TSB41AB2, TSB41AB2I

IEEE 1394a2000 TWOPORT CABLE

TRANSCEIVER/ARBITER

SLLS424G − JUNE 2000 − REVISED DECEMBER 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

interface reset and disable (continued)

If the LLC continues to keep the LPS signal deasserted, it requests that the interface be disabled. The PHY

disables the interface when it observes that LPS has been deasserted for TLPS_DISABLE. When the interface

is disabled, the PHY sets its CTL and D outputs as stated above for interface reset, but also stops SYSCLK

activity. The interface is also placed into the disabled condition upon a hardware reset of the PHY. The timing

for interface disable is shown in Figure 24 and Figure 25.

When the interface is disabled, the PHY enters a low-power state if none of its ports is active.

LPS

CTL0, CTL1

LREQ

SYSCLK

(3)

(2)

(1)

D0−D7

(low)

(4)

TLPSL

TLPSH

TLPS_RESET

TLPS_DISABLE

ISO

Figure 24. Interface Disable, ISO Low

The sequence of events for disabling the PHY-LLC interface when it is in the differentiated mode of operation

(ISO terminal is low) is as follows:

Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet data

reception and transmission via the CTL and D lines, and request activity via the LREQ line.

LPS deasserted. The LLC deasserts the LPS signal and, within 1

µs, terminates any request or interface

bus activity, and places its LREQ, CTL, and D outputs into a high-impedance state (the LLC should

terminate any output signal activity such that signals end in a logic 0 state).

Interface reset. After TLPS_RESET time, the PHY determines that LPS is inactive, terminates any interface

bus activity, and places its CTL and D outputs into a high-impedance state (the PHY terminates any output

signal activity such that signals end in a logic 0 state). The PHY-LLC interface is now in the reset state.

Interface disabled. If the LPS signal remains inactive for TLPS_DISABLE time, the PHY terminates SYSCLK

activity by placing the SYSCLK output into a high-impedance state. The PHY-LLC interface is now in the

disabled state.

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