TSB41AB2PAPG4 datasheet(18/55 Pages) TI1

18 / 55 page

TSB41AB2, TSB41AB2I

IEEE 1394a2000 TWOPORT CABLE

TRANSCEIVER/ARBITER

SLLS424G − JUNE 2000 − REVISED DECEMBER 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

Outer Shield Termination

Chassis GND

Figure 7. Nonisolated Outer Shield Termination

LPS

10 k

Ω

10 k

Ω

Link Power

Square Wave Input

Figure 8. Nonisolated Circuit Connection Variations for LPS

LPS

13.7 k

Ω

Square Wave Signal

10 k

Ω

PHY VDD

0.033

µF

PHY GND

NOTE: As long as the resistance ratio is maintained between 1.61:1 and

1.33:1, any values of resistors may be used.

Figure 9. Isolated Circuit Connection for LPS

crystal selection

The TSB41AB2 and other TI PHY devices are designed to use an external 24.576-MHz crystal connected

between the XI and XO terminals to provide the reference for an internal oscillator circuit. This oscillator in turn

drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data

at the S100 through S400 media data rates.

A variation of less than

±100 ppm from nominal for the media data rates is required by IEEE Std 1394. Adjacent

PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHYs must

be able to compensate for this difference over the maximum packet length. Larger clock variations may cause

resynchronization overflows or underflows, resulting in corrupted packet data.

For the TSB41AB2, the SYSCLK output may be used to measure the frequency accuracy and stability of the

internal oscillator and PLL from which it is derived. The frequency of the SYSCLK output must be within

±100 ppm of the nominal frequency of 49.152 MHz.

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