A3P030 datasheet(16/210 Pages) MICROSEMI

16 / 210 page

ProASIC3 Flash Family FPGAs

Re vi s i on 15

2 - 11

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For more

accurate and detailed power estimations, use the SmartPower tool in Libero SoC software.

The power calculation methodology described below uses the following variables:

•

The number of PLLs as well as the number and the frequency of each output clock generated

•

The number of combinatorial and sequential cells used in the design

•

The internal clock frequencies

•

The number and the standard of I/O pins used in the design

•

The number of RAM blocks used in the design

•

Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-16 on

page 2-13.

•

Enable rates of output buffers—guidelines are provided for typical applications in Table 2-17 on

page 2-13.

•

Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-17 on page 2-13. The calculation should be repeated for each clock domain defined in the

design.

Methodology

Total Power Consumption—PTOTAL

PTOTAL = PSTAT + PDYN

PSTAT is the total static power consumption.

PDYN is the total dynamic power consumption.

Total Static Power Consumption—PSTAT

PSTAT = PDC1 + NINPUTS* PDC2 + NOUTPUTS* PDC3

NINPUTS is the number of I/O input buffers used in the design.

NOUTPUTS is the number of I/O output buffers used in the design.

Total Dynamic Power Consumption—PDYN

PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL

Global Clock Contribution—PCLOCK

PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK

NSPINE is the number of global spines used in the user design—guidelines are provided in the "Spine

Architecture" section of the Global Resources chapter in the ProASIC3 FPGA Fabric User's Guide.

Table 2-15 • Different Components Contributing to the Static Power Consumption in ProASIC3 Devices

Parameter

Definition

Device Specific Static Power (mW)

PDC1

Array static power in Active mode

See Table 2-7 on page 2-6.

PDC2

I/O input pin static power (standard-dependent)

See Table 2-8 on page 2-6 through

Table 2-10 on page 2-7.

PDC3

I/O output pin static power (standard-dependent)

See Table 2-11 on page 2-8 through

Table 2-13 on page 2-9.

PDC4

Static PLL contribution

2.55 mW

PDC5

Bank quiescent power (VCCI-dependent)

See Table 2-7 on page 2-6.

Note:

*For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power

spreadsheet calculator or SmartPower tool in Libero SoC software.

A3P030 датащи(PDF) 16 Page - Microsemi Corporation

A3P030 датащи(HTML) 16 Page - Microsemi Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL