A3P030 datasheet(94/210 Pages) MICROSEMI

94 / 210 page

ProASIC3 Flash Family FPGAs

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Clock Conditioning Circuits

CCC Electrical Specifications

Timing Characteristics

Table 2-115 • ProASIC3 CCC/PLL Specification

Parameter

Minimum

Typical

Maximum

Units

Clock Conditioning Circuitry Input Frequency fIN_CCC

1.5

350

MHz

Clock Conditioning Circuitry Output Frequency fOUT_CCC

0.75

350

MHz

Serial Clock (SCLK) for Dynamic PLL1

125

MHz

Delay Increments in Programmable Delay Blocks2, 3

2004

Number of Programmable Values in Each Programmable

Delay Block

Input Period Jitter

1.5

CCC Output Peak-to-Peak Period Jitter FCCC_OUT

Max Peak-to-Peak Period Jitter

1 Global

Network

Used

3 Global

Networks

Used

0.75 MHz to 24 MHz

0.50%

0.70%

24 MHz to 100 MHz

1.00%

1.20%

100 MHz to 250 MHz

1.75%

2.00%

250 MHz to 350 MHz

2.50%

5.60%

Acquisition Time

(A3P250 and A3P1000 only)

LockControl = 0

300

µs

LockControl = 1

300

µs

(all other dies)

LockControl = 0

300

µs

LockControl = 1

6.0

Tracking Jitter 5

(A3P250 and A3P1000 only)

LockControl = 0

1.6

LockControl = 1

1.6

(all other dies)

LockControl = 0

1.6

LockControl = 1

0.8

Output Duty Cycle

48.5

51.5

Delay Range in Block: Programmable Delay 12, 3

0.6

5.56

Delay Range in Block: Programmable Delay 22, 3

0.225

5.56

Delay Range in Block: Fixed Delay2, 3

2.2

Notes:

1. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific junction

temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 for deratings.

3. TJ = 25°C, VCC = 1.5 V

4. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay

increments are available. Refer to the Libero SoC Online Help for more information.

5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock

edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter

parameter.

6. The A3P030 device does not contain a PLL.

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