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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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A3P030 датащи(PDF) 82 Page - Microsemi Corporation |
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A3P030 датащи(HTML) 82 Page - Microsemi Corporation |
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82 / 210 page  ProASIC3 Flash Family FPGAs Re vi s i on 15 2 - 77 Timing Characteristics Figure 2-20 • Input DDR Timing Diagram tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR tDDRICLR2Q1 12 3 4 5 6 7 8 9 CLK Data CLR Out_QR Out_QF tDDRICLKQ1 2 4 6 3 5 7 tDDRIHD tDDRISUD tDDRICLKQ2 Table 2-102 • Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.27 0.31 0.37 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.39 0.44 0.52 ns tDDRISUD Data Setup for Input DDR (Fall) 0.25 0.28 0.33 ns Data Setup for Input DDR (Rise) 0.25 0.28 0.33 ns tDDRIHD Data Hold for Input DDR (Fall) 0.00 0.00 0.00 ns Data Hold for Input DDR (Rise) 0.00 0.00 0.00 ns tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.46 0.53 0.62 ns tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.57 0.65 0.76 ns tDDRIREMCLR Asynchronous Clear Removal time for Input DDR 0.00 0.00 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery time for Input DDR 0.22 0.25 0.30 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.22 0.25 0.30 ns tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR 0.36 0.41 0.48 ns tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR 0.32 0.37 0.43 ns FDDRIMAX Maximum Frequency for Input DDR 350 309 263 MHz Note: For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating values. |
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