AT45DB321E datasheet(33/73 Pages) ETC2

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AT45DB321E

8784F–DFLASH–11/2013

10.2 Ultra-Deep Power-Down

The Ultra-Deep Power-Down mode allows the device to consume far less power compared to the standby and Deep

Power-Down modes by shutting down additional internal circuitry. Since almost all active circuitry is shutdown in this

mode to conserve power, the contents of the SRAM buffers cannot be maintained. Therefore, any data stored in the

SRAM buffers will be lost once the device enters the Ultra-Deep Power-Down mode.

When the device is in the Ultra-Deep Power-Down mode, all commands including the Status Register Read and Resume

from Deep Power-Down commands will be ignored. Since all commands will be ignored, the mode can be used as an

extra protection mechanism against program and erase operations.

Entering the Ultra-Deep Power-Down mode is accomplished by simply asserting the CS pin, clocking in the opcode 79h,

and then deasserting the CS pin. Any additional data clocked into the device after the opcode will be ignored. When the

CS pin is deasserted, the device will enter the Ultra-Deep Power-Down mode within the maximum time of tEUDPD.

The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on an

even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby mode

once the CS pin is deasserted. In addition, the device will default to the standby mode after a power cycle.

The Ultra-Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase

cycle is in progress. The Ultra-Deep Power-Down command must be reissued after the internally self-timed operation

has been completed in order for the device to enter the Ultra-Deep Power-Down mode.

Figure 10-3. Ultra-Deep Power-Down

SCK

MSB

ICC

Opcode

High-impedance

Ultra-Deep Power-Down Mode Current

Active Current

Standby Mode Current

tEUDPD

1111001

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