AT25DF081A datasheet(36/54 Pages) ETC2

36 / 54 page

8715C–SFLSH–1/2013

AT25DF081A

11.3 Write Status Register Byte 2

The Write Status Register Byte 2 command is used to modify the RSTE and SLE bits of the Status Register. Using

the Write Status Register Byte 2 command is the only way to modify the RSTE and SLE bits in the Status Register

during normal device operation, and the SLE bit can only be modified if the sector lockdown state has not been fro-

zen. Before the Write Status Register Byte 2 command can be issued, the Write Enable command must have been

previously issued to set the WEL bit in the Status Register to a logical “1”.

To issue the Write Status Register Byte 2 command, the CS pin must first be asserted and the opcode of 31h must

be clocked into the device followed by one byte of data. The one byte of data consists of three don’t care bits, the

RSTE bit value, the SLE bit value, and three additional don’t care bits (see Table 11-4). Any additional data bytes

that are sent to the device will be ignored. When the CS pin is deasserted, the RSTE and SLE bits in the Status

only be modified if the Freeze Sector Lockdown State command has not been previously issued.

The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin

must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation,

the state of the RSTE and SLE bits will not change, and the WEL bit in the Status Register will be reset back to the

logical “0” state.

Figure 11-3. Write Status Register Byte 2

Table 11-4.

Write Status Register Byte 2 Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RSTE

SLE

SCK

MSB

0011000

OPCODE

10 11

814 15

MSB

XXX

STATUS REGISTER IN

BYTE 2

HIGH-IMPEDANCE

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