AT25DF081A datasheet(18/54 Pages) ETC2

номер детали	AT25DF081A

подробное описание детали	8-Mbit 2.7V Minimum SPI Serial Flash Memory

PDF	54 Pages

Scroll/Zoom	100%

производитель	ETC2 [List of Unclassifed Manufacturers]

домашняя страница

Logo

18 / 54 page

8715C–SFLSH–1/2013

AT25DF081A

9.2

Write Disable

The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Register to the logical

"0" state. With the WEL bit reset, all Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector Lock-

down, Freeze Sector Lockdown State, Program OTP Security Register, and Write Status Register commands will

not be executed. Other conditions can also cause the WEL bit to be reset; for more details, refer to the WEL bit

section of the Status Register description.

To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h must be clocked

into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will

be ignored. When the CS pin is deasserted, the WEL bit in the Status Register will be reset to a logical “0”. The

complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deas-

serted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the

state of the WEL bit will not change.

Figure 9-2.

Write Disable

SCK

MSB

00000100

OPCODE

HIGH-IMPEDANCE

AT25DF081A датащи(PDF) 18 Page - List of Unclassifed Manufacturers