AD9775 datasheet(24/56 Pages) AD

24 / 56 page

AD9775

Rev. E | Page 24 of 56

DAC OPERATION

The dual, 14-bit DAC output of the AD9775, along with the

reference circuitry, gain, and offset registers, is shown in Figure 37.

Note that an external reference can be used by simply overdriving

the internal reference with the external reference. Referring to the

transfer functions in Equation 1, a reference current is set by the

internal 1.2 V reference, the external RSET resistor, and the values

in the coarse gain register. The fine gain DAC subtracts a small

amount from this and the result is input to IDAC and QDAC,

where it is scaled by an amount equal to 1024/24. Figure 38 and

Figure 39 show the scaling effect of the coarse and fine adjust

DACs. IDAC and QDAC are PMOS current source arrays,

segmented in a 5-4-5 configuration. The 5 MSBs control an array

of 31 current sources. The next four bits consist of 15 current

sources whose values are all equal to 1/16 of an MSB current

source. The 5 LSBs are binary weighted fractions of the middle

bits’ current sources. All current sources are switched to either

IOUTA or IOUTB, depending on the input code.

The fine adjustment of the gain of each channel allows for

improved balance of QAM modulated signals, resulting in

improved modulation accuracy and image rejection.

In the section Interfacing the AD9775 with the AD8345

Quadrature Modulator, the performance data shows to what

degree image rejection can be improved when the AD9775 is

used with an AD8345 quadrature modulator from Analog

Devices, Inc.

μA

0.7V

REFIO

AVDD

Figure 37. Equivalent Internal Reference Circuit

2R MODE

1R MODE

COARSE GAIN REGISTER CODE

(ASSUMING RSET1, RSET2 = 1.9k

Ω)

010

Figure 38. Coarse Gain Effect on IFULLSCALE

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

1R MODE

2R MODE

FINE GAIN REGISTER CODE

(ASSUMING RSET1, RSET2 = 1.9k

Ω)

200

400

600

800

1000

Figure 39. Fine Gain Effect on IFULLSCALE

FINE

GAIN

DAC

FINE

GAIN

DAC

COARSE

GAIN

DAC

COARSE

GAIN

DAC

OFFSET

DAC

OFFSET

DAC

GAIN

CONTROL

REGISTERS

OFFSET

CONTROL

REGISTERS

GAIN

CONTROL

REGISTERS

OFFSET

CONTROL

REGISTERS

1.2VREF

IDAC

QDAC

REFIO

0.1

μF

FSADJ1

RSET1

IOUTA1

IOUTA2

IOUTB1

IOUTB2

RSET2

FSADJ2

Figure 40. DAC Outputs, Reference Current Scaling, and Gain/Offset Adjust

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