PD488588FF datasheet(49/79 Pages) ELPIDA

49 / 79 page

Data Sheet

E0251N20 (Ver. 2.0)

µµµµPD488588FF-C80-40

Once the RDRAM is in ATTN, ATTNW, or ATTNR states, it will remain there until it is explicitly returned to the STBY

state with a RLX command. A RLX command may be given in an ROWR, COLC, or COLX packet (see the left side

of Figure 23-2). It is usually given after all banks of the RDRAM have been precharged; if other banks are still

activated, then the RLX command would probably not be given.

If a broadcast ROWA packet or ROWR packet (with the ATTN command) is received, the RDRAM’s power state

doesn’t change. If a broadcast ROWR packet with RLXR command is received, the RDRAM goes to STBY.

Figure 23-2 STBY Entry (left) and STBY Exit (right)

STBY

ATTN

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

T12

T13

T10

T14

T11

T15 T16

T20

T17

T21

T18

T22

T19

T23

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

T12

T13

T10

T14

T11

T15 T16

tAS

RLXR

Power

State

ATTN

Power

State

STBY

tSA

ROP a0

RLXC

RLXX

TFRM•tCYCLE

COP a1

XOP a1

COP a0

XOP a0

ROP=non-broadcast

ROWA or ROWR/ATTN

a0={d0, b0, r0}

a1={d1, b1, c1}

No COL packets may be

placed in the three

indicated positions; i.e. at

(TFRM-{1,2,3})•tCYCLE.

A COL packet to device d0

(or any other device) is okay at

(TFRM)•tCYCLE

or later.

A COL packet to another device

(d1!=d0) is okay at

(TFRM-4)•tCYCLE

or earlier.

Figure 23-3 shows the NAP entry sequence (left). NAP state is entered by sending a NAPR command in a ROW

packet. A time tASN is required to enter NAP state (this specification is provided for power calculation purposes). The

clock on CTM/CFM must remain stable for a time tCD after the NAPR command.

Figure 23-3 NAP Entry (left) and PDN Entry (right)

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

T12

T13

T10

T14

T11

T15 T16

T20

T17

T21

T18

T22

T19

T23

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

T12

T13

T10

T14

T11

tASN

ROP a0

(NAPR)

Power

State

ATTN/STBYNote

Power

State

NAP

ATTN/STBY Note

PDN

tASP

ROP a0

(PDNR)

Note The(eventual) NAP/PDN exit will be to the same ATTN/STBY state the RDRAM was in prior to NAP/PDN entry

tCD

a0={d0, b0, r0, c0}

a1={d1, b1, c1, c1}

No ROW or COL packets directed

to device d0 may overlap the

restricted interval. No broadcast

ROW packets may overlap

the quiet interval.

ROW or COL packets to a device

other than d0 may overlap the

restricted interval.

restricted

ROP a1

COP a0

XOP a0

COP a1

XOP a1

restricted

ROP a1

COP a0

XOP a0

COP a1

XOP a1

restricted

ROW or COL packets directed

to device d0 after the restricted

interval will be ignored.

tNPQ

The RDRAM may be in ATTN or STBY state when the NAPR command is issued. When NAP state is exited, the

RDRAM will return to the original starting state (ATTN or STBY). If it is in ATTN state and a RLXR command is

specified with NAPR, then the RDRAM will return to STBY state when NAP is exited.

Figure 23-3 also shows the PDN entry sequence (right). PDN state is entered by sending a PDNR command in a

ROW packet. A time tASP is required to enter PDN state (this specification is provided for power calculation

purposes). The clock on CTM/CFM must remain stable for a time tCD after the PDNR command.

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