PD488588FF datasheet(33/79 Pages) ELPIDA

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Data Sheet

E0251N20 (Ver. 2.0)

µµµµPD488588FF-C80-40

20. Control Register Packets

Table 20-1 summarizes the formats of the four packet

types for control register transactions. Table 20-2

summarizes the fields that are used within the packets.

Figure 20-1 shows the transaction format for the SETR,

CLRR, and SETF commands. These transactions consist

of a single SRQ packet, rather than four packets like the

SWR and SRD commands. The same framing sequence

on the CMD input is used, however. These commands are

used during initialization prior to any control register read

or write transactions.

Table 20-1 Control Register Packet Formats

SCK

Cycle

SIO0 or

SIO1

for SRQ

SIO0 or

SIO1

for SA

SIO0 or

SIO1

for SINT

SIO0 or

SIO1

for SD

SCK

Cycle

SIO0 or

SIO1

for SRQ

SIO0 or

SIO1

for SA

SIO0 or

SIO1

for SINT

SIO0 or

SIO1

for SD

rsrv

SD15

SOP1

SA7

SD7

rsrv

SD14

SOP0

SA6

SD6

rsrv

SD13

SBC

SA5

SD5

rsrv

SD12

SDEV4

SA4

SD4

rsrv

SA11

SD11

SDEV3

SA3

SD3

SDEV5

SA10

SD10

SDEV2

SA2

SD2

SOP3

SA9

SD9

SDEV1

SA1

SD1

SOP2

SA8

SD8

SDEV0

SA0

SD0

Table 20-2 Field Description for Control Register Packets

Field

Description

rsrv

Reserved. Should be driven as “0” by controller.

SOP3..SOP0

0000 - SRD. Serial read of control register {SA11..SA0} of RDRAM {SDEV5..SDEV0}.

0001 - SWR. Serial write of control register {SA11..SA0} of RDRAM {SDEV5..SDEV0}.

0010 - SETR. Set Reset bit, all control registers assume their reset values.

Note 16 tSCYCLE delay until CLRR

command.

0100 - SETF. Set fast (normal) clock mode. 4 tSCYCLE delay until next command.

1011 - CLRR. Clear Reset bit, all control registers retain their reset values.

Note 4 tSCYCLE delay until next

command.

1111 - NOP. No serial operation.

0011, 0101 – 1010, 1100 – 1110 – RSRV. Reserved encodings.

SDEV5..SDEV0

Serial device. Compared to SDEVID5..SDEVID0 field of INIT control register field to select the RDRAM to

which the transaction is directed.

SBC

Serial broadcast. When set, RDRAMs ignore {SDEV5..SDEV0} for RDRAM selection.

SA11..SA0

Serial address. Selects which control register of the selected RDRAM is read or written.

SD15..SD0

Serial data. The 16 bits of data written to or read from the selected control register of the selected RDRAM.

Note The SETR and CLRR commands must always be applied in two successive transactions to RDRAMs; i.e. they may not be

used in isolation. This is called “SETR/CLRR Reset”.

Figure 20-1 SETR, CLRR, SETF Transaction

SCK

CMD

SIO0

T20

SRQ packet - SETR/CLRR/SETF

1111

00000000...00000000

SRQ packet - SETR/CLRR/SETF

0000

SIO1

The packet is repeated

from SIO0 to SIO1

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