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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PD488588FF датащи(PDF) 62 Page - Elpida Memory |
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PD488588FF датащи(HTML) 62 Page - Elpida Memory |
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62 / 79 page  Data Sheet E0251N20 (Ver. 2.0) 62 µµµµPD488588FF-C80-40 33. CMOS - Receive Timing Figure 33-1 is a timing diagram which shows the detailed requirements for the CMOS input signals. The CMD and SIO0 signals are inputs which receive information transmitted by a controller (or by another RDRAM’s SIO1 output). SCK is the CMOS clock signal driven by the controller. All signals are high true. The cycle time, high phase time, and low phase time of the SCK clock are tCYCLE1, tCH1 and tCL1, all measured at the 50 % level. The rise and fall times of SCK, CMD, and SIO0 are tDR1 and tDF1, measured at the 20 % and 80 % levels. The CMD signal is sampled twice per tCYCLE1 interval, on the rising edge (odd data) and the falling edge (even data). The set/hold window of the sample points is tS1/tH1. The SCK and CMD timing points are measured at the 50 % level. The SIO0 signal is sampled once per tCYCLE1 interval on the falling edge. The set/hold window of the sample points is tS2/tH2. The SCK and SIO0 timing points are measured at the 50 % level. Figure 33-1 CMOS Timing - Data Signals for Receive VIH,CMOS 80% 50% 20% V IL,CMOS SCK even odd VIH,CMOS 80% 20% VIL,CMOS CMD tDR2 t DF2 tS1 50% t DR2 t DF2 CYCLE1 t CH1 t CL1 t tH1 tS1 tH1 V IH,CMOS 80% 20% VIL,CMOS SIO0 t DR1 t DF1 tS2 50% tH2 |
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