DS2154 datasheet(4/87 Pages) DALLAS

4 / 87 page

DS2154

4 of 87

1.0 INTRODUCTION

The DS2154 is a super-set version of the popular DS2153 E1 Single-Chip Transceiver offering the new

features listed below. All of the original features of the DS2153 have been retained and software created

for the original devices is transferable into the DS2154.

NEW FEATURES

SECTION

Option for non-multiplexed bus operation

1 and 2

Crystal-less jitter attenuation

Additional hardware signaling capability including:

Receive signaling reinsertion to a backplane multiframe sync

Availability of signaling in a separate PCM data stream

Signaling freezing

Interrupt generated on change of signaling data

Improved receive sensitivity: 0 dB to -43 dB

Per-channel code insertion in both transmit and receive paths

Expanded access to Sa and Si bits

RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state

8.192 MHz clock synthesizer

Per-channel loopback

Addition of hardware pins to indicate carrier loss and signaling freeze

Line interface function can be completely decoupled from the framer/formatter to

allow:

Interface to optical, HDSL, and other NRZ interfaces

“tap” the transmit and receive bipolar data streams for monitoring purposes

Be able corrupt data and insert framing errors, CRC errors, etc.

Transmit and receive elastic stores now have independent backplane clocks

Ability to monitor one DS0 channel in both the transmit and receive paths

Access to the data streams in between the framer/formatter and the elastic stores

AIS generation in the line interface that is independent of loopbacks

1 and 3

Transmit current limiter to meet the 50 mA short circuit requirement

Option to extend carrier loss criteria to a 1 ms period as per ETS 300 233

Automatic RAI generation to ETS 300 011 specifications

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