DS2154 datasheet(2/87 Pages) DALLAS

2 / 87 page

DS2154

2 of 87

TABLE OF CONTENTS

1.0

INTRODUCTION ............................................................................................................. 4

New Features................................................................................................................................... 4

Block Diagram ................................................................................................................................ 5

Pin List ............................................................................................................................................ 7

Pin Description.............................................................................................................................. 10

Register Map ................................................................................................................................. 15

2.0

PARALLEL PORT ........................................................................................................ 20

3.0

CONTROL, ID, AND TEST REGISTERS...................................................................... 20

SYNC/RESYNC Criteria.............................................................................................................. 22

Framers Loopback......................................................................................................................... 27

Automatic Alarm Generation........................................................................................................ 28

Power-up Sequence....................................................................................................................... 30

Remote Loopback ......................................................................................................................... 31

Local Loopback............................................................................................................................. 31

4.0

STATUS AND INFORMATION REGISTERS................................................................ 32

CRC 4 SYNC Counter .................................................................................................................. 35

Alarm Criteria ............................................................................................................................... 36

5.0

ERROR COUNT REGISTERS ...................................................................................... 40

BPV or Code Violation Counter ...................................................................................................40

CRC4 Error Counter ..................................................................................................................... 41

E-bit Counter................................................................................................................................. 41

FAS Error Counter ........................................................................................................................ 42

6.0

DSO MONITORING FUNCTION ................................................................................... 43

7.0

SIGNALING OPERATION ............................................................................................ 46

Processor Based Signaling ............................................................................................................ 46

Hardware Based Signaling............................................................................................................ 49

8.0

PER-CHANNEL CODE GENERATION ........................................................................ 51

Transmit Side Code Generation .................................................................................................... 51

Receive Side Code Generation ..................................................................................................... 53

9.0

CLOCK BLOCKING REGISTERS ................................................................................ 54

10.0

ELASTIC STORES OPERATION ................................................................................. 56

11.0

ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION .............................. 57

Hardware Scheme ......................................................................................................................... 57

Internal Register Scheme Based on Double-Frame ...................................................................... 57

Internal Register Scheme Based on CRC4 Multiframe ................................................................ 60

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