DS2154 datasheet(13/87 Pages) DALLAS

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DS2154

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Receive Negative Data Input [RNEGI]. Sampled on the falling edge of RCLKI for data to be clocked

through the receive side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be

internally connected to RNEGO by tying the LIUC pin high.

Receive Clock Input [RCLKI]. Clock used to clock data through the receive side framer. This pin is

normally tied to RCLKO. Can be internally connected to RCLKO by tying the LIUC pin high. RCLKI

must be present for the parallel control port to operate properly.

PARALLEL CONTROL PORT PINS

Interrupt [INT]. Flags host controller during conditions and change of conditions defined in the Status

Registers 1 and 2. Active low, open drain output.

3-State Control [Test]. Set high to 3-state all output and I/O pins (including the parallel control port). Set

low for normal operation. Useful in board level testing.

Bus Operation [MUX]. Set low to select non-multiplexed bus operation. Set high to select multiplexed

bus operation.

Data Bus [D0 to D7] or Address/Data Bus [AD0 to AD7]. In non-multiplexed bus operation (MUX=0),

serves as the data bus. In multiplexed bus operation (MUX=1), serves as a 8-bit multiplexed address /

data bus.

Address Bus [A0 to A6]. In non-multiplexed bus operation (MUX=0), serves as the address bus. In

multiplexed bus operation (MUX=1), these pins are not used and should be tied low.

Bus Type Select [BTS]. Strap high to select Motorola bus timing; strap low to select Intel bus timing.

This pin controls the function of the RD\(DS), ALE(AS), and WR\(R/W\) pins. If BTS=1, then these pins

assume the function listed in parenthesis ().

Read Input [ RD ] (Data Strobe [ DS ]). RD and DS are active low signals when MUX=11. DS is active

high when MUX = 0. See bus timing diagrams.

Chip Select [CS]. Must be low to read or write to the device. CS is an active low signal.

A7 or Address Latch Enable [ALE] (Address Strobe [AS]). In non-multiplexed bus operation

(MUX=0), serves as the upper address bit. In multiplexed bus operation (MUX=1), serves to demultiplex

the bus on a positive-going edge.

Write Input [WR] (Read/Write [R/W]). WR is an active low signal.

LINE INTERFACE PINS

Master Clock Input [MCLK]. 2.048 MHz (± 50 ppm) clock source with TTL levels is applied at this

pin. This clock is used internally for both clock/data recovery and for jitter attenuation. A quartz crystal

of 2.048 MHz may be applied across MCLK and XTALD instead of the TTL level clock source.

Quartz Crystal Driver [XTALD]. A quartz crystal of 2.048 MHz may be applied across MCLK and

XTALD instead of a TTL level clock source at MCLK. Leave open circuited if a TTL clock source is

applied at MCLK.

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