CY7C0430V
PRELIMINARY
25
address the entire memory array (depend on the value of
the mask register) and loop back to location 0. The incre-
ment operation is second in priority to load operation.
3. Readback: the internal value of either the burst counter or
the mask register can be read out on the address lines when
CNTRD or MKRD is LOW. Counter readback has higher
priority over mask register readback. A no-operation delay
cycle is experienced when readback operation is per-
formed. The address will be valid after tCA2 (for counter
readback) or tCM2 (for mask readback) from the following
port's clock rising edge. Address readback operation is in-
dependent of the port's chip enables (CE0 and CE1). If ad-
dress readback occurs while the port is enabled (chip en-
ables active), the data lines (I/Os) will be three-stated.
4. Hold operation: In order to hold the value of the address
counter at certain address, all signals in Table 2 have to be
HIGH. This operation has the least priority. This operation
is useful in many applications where wait states are needed
or when address is available few cycles ahead of data.
The counter and mask register operations are totally indepen-
dent of port chip enables.
IEEE 1149.1 Serial Boundary Scan (JTAG) and
Memory Built-In-Self-Test (MBIST)
The CY7C0430V incorporates a serial boundary scan test ac-
cess port (TAP). This port operates in accordance with IEEE
Standard 1149.1-1900. Note that the TAP controller functions
in a manner that does not conflict with the operation of other
devices using 1149.1 fully compliant TAPs. The TAP operates
using JEDEC standard 3.3V I/O logic levels. It is composed of
three input connections and one output connection required by
the test logic defined by the standard. Memory BIST circuitry
will also be controlled through the TAP interface. All MBIST
instructions are compliant to the JTAG standard. An external
clock (CLKBIST) is provided to allow the user to run BIST at
speeds higher than 100 MHz. CLKBIST is multiplexed internal-
ly with the ports clocks during BIST operation.
Disabling the JTAG Feature
It is possible to operate the QuadPort without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are in-
ternally pulled up and may be unconnected. They may alter-
nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. CLKBIST must be tied LOW to
disable the MBIST. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
Test Access Port (TAP) - Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the regis-
ters and can be connected to the input of any of the registers.
The register between TDI and TDO is chosen by the instruc-
tion that is loaded into the TAP instruction register. For infor-
mation on loading the instruction register, see the TAP Con-
troller State Diagram. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Test Data Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see TAP Controller State Dia-
gram (FSM)). The output changes on the falling edge of TCK.
TDO is connected to the least significant bit (LSB) of any reg-
ister.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
QuadPort and may be performed while the device is operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the QuadPort test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Instruction Register
Four-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the following JTAG/BIST Con-
troller diagram. Upon power-up, the instruction register is load-
ed with the IDCODE instruction. It is also loaded with the
IDCODE instruction if the controller is placed in a reset state
as described in the previous section.
When the TAP controller is in the CaptureIR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain devices. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
QuadPort with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the QuadPort. The boundary scan register is
loaded with the contents of the QP Input and Output ring when
the TAP controller is in the Capture-DR state and is then
placed between the TDI and TDO pins when the controller is
moved to the Shift-DR state. The EXTEST, and SAM-
PLE/PRELOAD instructions can be used to capture the con-
tents of the Input and Output ring.
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