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CY7C0430V датащи(PDF) 19 Page - Cypress Semiconductor

номер детали CY7C0430V
подробное описание детали  3.3V 64K x 18 Synchronous QuadPort??Static RAM
PDF  36 Pages
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производитель  CYPRESS [Cypress Semiconductor]
домашняя страница  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C0430V датащи(HTML) 19 Page - Cypress Semiconductor

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CY7C0430V
PRELIMINARY
19
Port 1 Write to Port 2 Read[29, 30, 31]
Notes:
29. CE0 = OE = LB = UB = CNTLD =VIL; CE1 = CNTRST = MRST = MKLD = MKRD = CNTRD = CNTINC =VIH.
30. This timing is valid when one port is writing, and one or more of the three other ports is reading the same location at the same time. If tCCS is violated, indeterminate
data will be read out.
31. If tCCS< minimum specified value, then Port 2 will read the most recent data (written by Port 1) only (2*tCYC2 + tCD2) after the rising edge of Port 2's clock. If tCCS
> minimum specified value, then Port 2 will read the most recent data (written by Port 1) (tCYC2 + tCD2) after the rising edge of Port 2's clock.
Switching Waveforms (continued)
tSA
tHA
tSW
tHW
tCH2
tCL2
tCYC2
CLKP1
R/WP1
An
Dn
tCKHZ
tHD
tSA
An
tHA
Qn
tDC
tCCS
tSD
tCKLZ
tCH2
tCL2
tCYC2
tCD2
PORT-1
ADDRESS
PORT-1
DATAIN
CLKP2
R/WP2
PORT-2
ADDRESS
PORT-2
DATAOUT



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