CS5361

16

MCLK=12.288 MHz; Master Mode)

Notes: 5. Power Down Mode is defined as RST = Low with all clocks and data lines held static.

6. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection

Diagram.

DIGITAL CHARACTERISTICS

Parameter

Symbol

Min

Typ

Max

Unit

DC Power Supplies:

Positive Analog

Positive Digital

Positive Logic

VA

VD

VL

4.75

3.1

2.37

5.0

-

-

5.25

5.25

5.25

V

V

V

Power Supply Current

VA

(Normal Operation)

VL,VD = 5 V

VL,VD = 3.3V

-

-

-

17.5

22

14.5

21

26

17

mA

mA

mA

Power Supply Current

VA

(Power-Down Mode)(Note 5)

VL,VD=5V

-

-

2

2

-

-

mA

mA

Power Consumption

(Normal Operation)

VL, VD=5V

VL, VD = 3.3V

(Power-Down Mode)

-

-

-

-

-

-

198

135

20

235

161

-

mW

mW

mW

Power Supply Rejection Ratio (1 kHz)

(Note 6)

PSRR

-

65

-

dB

Output Impedance

Maximum allowable DC current source/sink

-

-

-

2.5

25

0.01

-

-

-

V

k

Ω

mA

Filt+ Nominal Voltage

Output Impedance

Maximum allowable DC current source/sink

-

-

-

5

18

0.01

-

-

-

V

k

Ω

mA

Parameter

Symbol

Min

Typ

Max

Units

High-Level Input Voltage

(% of VL)

70%

-

-

V

Low-Level Input Voltage

(% of VL)

--

30%

V

(% of VL)

70%

-

-

V

(% of VL)

--

15%

V

OVFL Current Sink

--

4.0

mA

Input Leakage Current

--

±10

µA