CS5361

6

3 APPLICATIONS

3.1

Operational Mode/Sample Rate Range Select

The output sample rate, Fs, can be adjusted from 2kHz to 192kHz. The CS5361 must be set to the proper

speed mode via the mode pins, M1 and M0. Refer to Table 1.

3.2

System Clocking

The device supports operation in either Master Mode, where the left/right and serial clocks are synchro-

nously generated on-chip, or Slave Mode, which requires external generation of the left/right and serial

clocks. The device also includes a master clock divider in Master Mode where the master clock will be

internally divided prior to any other internal circuitry when MDIV is enabled, set to logic 1. In Slave Mode,

the MDIV pin needs to be disabled, set to logic 0.

M1 (Pin 14) M0 (Pin 13)

MODE

Output Sample Rate (Fs)

0

0

Single Speed Mode

2kHz - 50kHz

0

1

Double Speed Mode

50kHz - 100kHz

1

0

Quad Speed Mode

100kHz - 192kHz

11

Reserved

Table 1. CS5361 Mode Control