CS4953 datasheet(36/44 Pages) CIRRUS

36 / 44 page

CS4952/53

DS223PP2

BOARD DESIGN & LAYOUT

CONSIDERATIONS

The printed circuit layout should be optimized for

lowest noise on the CS4952/3 power and ground

lines. Digital and analog sections should be physi-

cally separated and the CS4952/3 placed as close to

the output connectors as possible. All analog sup-

ply traces should be as short as possible to mini-

mize inductive ringing.

A well designed power distribution network is es-

sential in eliminating digital switching noise. The

ground planes must provide a low-impedance re-

turn path for the digital circuits. A PC board with a

minimum of four layers is recommended. The

ground layer should be used as a shield to isolate

noise from the analog traces. The top layer (1)

should be reserved for analog traces but digital

traces may share this layer if the digital signals

have low edge rates and switch little current or if

they are separated from the analog traces by a sig-

nificant distance (dependent on their frequency

content and current). The second layer should then

be the ground plane followed by the analog power

plane on layer three and the digital signal layer on

layer four

Power and Ground Planes

The power and ground planes need isolation gaps

of at 0.05” to minimize digital switching noise ef-

fects on the analog signals and components. A split

analog/digital ground plane should be connected at

one point as close as possible to the CS4952/3. A

split analog/digital power plane should be connect-

ed at one point as close as possible to the power en-

try point and decoupled properly.

Power Supply Decoupling

Start by reducing power supply ripple and wiring

harness inductance by placing a large (33 - 100uF)

capacitor as close to the power entry point as pos-

sible. Use separate power planes or traces for the

digital and analog sections even if they use the

same supply. If necessary, further isolate the digital

and analog power supplies by using ferrite beads on

each supply branch followed by a low ESR capac-

itor.

Place all decoupling caps as close as possible to the

device as possible. Surface mount capacitors gen-

erally have lower inductance than radial lead or ax-

ial lead components. Surface mount caps should be

placed on the component side of the PCB to mini-

mize inductance caused by board vias. Any vias,

especially to ground, should be as large as practical

to reduce their inductive effects.

VREF Decoupling

The VREFOUT pin provides a 1.235 V reference

for the internal DACs. VREFOUT is only intended

to drive VREFIN. Do not connect to an external

load. A small bypass cap, however, may be placed

on VREFOUT to reduce noise. Usually a 0.1uF

MLC surface mount capacitor is sufficient.

Digital Interconnect

The digital inputs and outputs of the CS4952/3

should be isolated from the analog outputs as much

as possible. Use separate signal layers whenever

possible and do not route digital signals over the

analog power and ground planes.

Noise from the digital section is directly related to

the digital edge rates used. Ringing, overshoot, un-

dershoot, and ground bounce are all related to edge

rate. Use lower speed logic such as HCMOS for the

host port interface to reduce switching noise. For

the video input ports, higher speed logic is re-

quired, but use the slowest practical edge rate to re-

duce noise.

To reduce digital noise, it is important to match the

source impedance, line impedance, and load im-

pedance as much as possible. Generally, if the line

length is greater than one fourth the signal edge

rate, line termination is necessary. Ringing may

also be reduced by damping the line with a series

resistor (22 - 150

Ω). Under extreme cases, it may

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