CS4923 datasheet(47/56 Pages) CIRRUS

47 / 56 page

CS4923/4/5/6/7/8/9

DS262F2

In parallel host mode, the CS4923/4/5/6/7/8/9 can

accept PCM data written through the byte-wide

host interface to address 10b (A1 high, A0 low). In

this mode, there is a close connection between the

CS4923/4/5/6/7/8/9 application code and the host

processor that is delivering the PCM data. The

PCMRST bit of the CONTROL register provides

absolute software/hardware synchronization by

initializing the input channel to uniquely recognize

the first write to the byte-wide PCMDATA port.

Toggling PCMRST high and low informs the DSP

that the next sample read from the PCMDATA port

is the first sample of the left channel. In this

fashion, the CS492X can translate successive byte

writes into a variable number of channels with a

variable PCM sample size. In the most simple case,

the CS492X can receive stereo 8-bit PCM one byte

at a time with the internal DSP assigning the first

8-bit write (after PCMRST) to the left channel and

the second 8-bit write to the right channel. For

16-bit PCM, it assigns the first two 8-bit writes

(after PCMRST) to the left channel and the next

two writes to the right channel.

7.5 Digital Audio Output Port

The Digital Audio Output port, or DAO, is the port

used for digital output from the DSP. Table 12

shows the signals associated with the DAO. As

there

are

many

modes

that

are

firmware

configurable on the DAO, please consult the

Hardware User’s Guide and the application code

user’s guides to determine which modes are

supported by the download code being used.

MCLK is the master clock and is firmware

configurable to be either an input or an output. If

MCLK is to be used as an output, the internal PLL

must be used. As an output MCLK can be

configured to provide a 128Fs, 256Fs or 512Fs

clock, where Fs is the output sample rate.

SCLK is the bit clock used to clock data out on

AUDATA0, AUDATA1 and AUDATA2. LRCLK

is the data framing clock whose frequency is

typically equal to the sampling frequency. Both

LRCLK and SCLK can be configured as either

inputs (Slave mode) or outputs (Master mode).

When LRCLK and SCLK are configured as inputs,

MCLK is a don’t care as an input. When LRCLK

and SCLK are configured as outputs, they are

derived

from

MCLK.

Whether

MCLK

configured as an input or an output, an internal

divider from the MCLK signal is used to produce

LRCLK and SCLK. The ratios shown in table 13

give the possible SCLK values for different MCLK

frequencies (all values in terms of the sampling

frequency, Fs).

AUDAT0 is configurable to provide six, four, or

two channels. AUDAT1 and AUDAT2 can both

output two channels of data. Typically all three

AUDAT outputs are used in left justified, I2S or

right justified modes. In this way all six channels of

surround (Left, Center, Right, Left Surround, Right

Surround

and

Subwoofer)

are

provided.

Alternatively the multi-channel mode can be

configured to provide single data line multi-

channel support. Please consult the Hardware

User’s Guide and the application code user’s

Pin Name

Pin Description

Pin Number

AUDAT2

Serial Data In

AUDAT1

Serial Data In

AUDAT0

Serial Data In

LRCLK

Frame Clock

SCLK

Serial Bit Clock

MCLK

Master Clock

XMT958

IEC60958 Transmitter

Table 12. Digital Audio Output Port

MCLK

(Fs)

SCLK (Fs)

128

256

512

128

384**

256

512

XXXX

** For MCLK as an input only

Table 13. MCLK/SCLK Master Mode Ratios

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