CS4923 datasheet(10/56 Pages) CIRRUS

10 / 56 page

CS4923/4/5/6/7/8/9

DS262F2

SWITCHING CHARACTERISTICS—MOTOROLA® HOST MODE

(TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Notes: 3. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can

be defined as follows:

External CLKIN Mode:

DCLK == CLKIN/3 before and during boot

DCLK == CLKIN after boot

Internal Clock Mode:

DCLK == 10MHz before and during boot, i.e. DCLK == 100ns

DCLK == 60 MHz after boot, i.e. DCLK == 16.7ns (this speed may depend on CLKIN, please see

CS4923/4/5/6/7/8/9 Hardware Users Guide for more information)

4. This specification is characterized but not production tested.

Parameter

Symbol

Min

Max

Unit

Address setup before CS and DS low

Tmas

Address hold time after CS and DS low

Tmah

Delay between DS then CS low or CS then DS low

Tmcdr

∞

Data valid after CS and DS low with R/W high

Tmdd

-20

CS and DS low for read

(Note 3)

Tmrpw

DCLK + 10

Data hold time after CS or DS high after read

Tmdhr

Data high-Z after CS or DS high low after read

(Note 4)

Tmdis

-15

CS or DS high to CS and DS low for next read

(Note 3)

Tmrd

2*DCLK + 10

CS or DS high to CS and DS low for next write

(Note 3)

Tmrdtw

2*DCLK + 10

Delay between DS then CS low or CS then DS low

Tmcdw

∞

Data setup before CS or DS high

Tmdsu

CS and DS low for write

(Note 3)

Tmwpw

DCLK + 10

R/W setup before CS or DS low

Tmrwsu

R/W hold time after CS or DS high

Tmrwhld

Data hold after CS or DS high

Tmdhw

CS or DS high to CS and DS low with R/W high for next read

(Note 3)

Tmwtrd

2*DCLK + 10

CS or DS high to CS and DS low for next write

(Note 3)

Tmwd

2*DCLK + 10

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