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CS42L50 датащи(PDF) 18 Page - Cirrus Logic |
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CS42L50 датащи(HTML) 18 Page - Cirrus Logic |
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18 / 48 page ![]() CS42L50 18 DS544PP1 4. REGISTER DESCRIPTION 4.1 ADC (Address = 0010000) 4.1.1 I/O and Power Control (address 01h) 4.1.2 20DB GAIN BOOST (BOOST) Default = 0 0 - Disabled 1 - Enabled Function: Applies a 20dB digital gain to the input signal, regardless of the input path. 4.1.3 ANALOG INPUT MULTIPLEXER (AINMUX) Default = 00 00 - Channel 1 direct to A/D 01 - Channel 2 direct to A/D 10 - Channel 2 through PGA to A/D 11 - Reserved Function: The analog input multiplexer selects the input channel as well as the input path ass ociated with various gain stages. 4.1.4 POWER DOWN (PDN) Default - 1 0 - Disabled 1 - Enabled Function: The entire ADC device will enter a low-power state whenever this function is activated. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation will begin. The con- tents of the control registers are retained when this mode is enabled. 4.1.5 CONTROL PORT ENABLE (CP_EN) Default = 0 0 - Disabled 1 - Enabled Function: The ADC will enter control port mode when this bit is enabled. This bit must be set prior to writing to the control port. 765 4321 0 RESERVED BOOST AINMUX1 AINMUX0 RESERVED RESERVED PDN CP_EN 000 0001 0 |
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