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CS42L50 датащи(PDF) 12 Page - Cirrus Logic

номер детали CS42L50
подробное описание детали  Low Voltage, Stereo CODEC with headphone Amp
PDF  48 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS42L50 датащи(HTML) 12 Page - Cirrus Logic

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CS42L50
12
DS544PP1
SWITCHING CHARACTERISTICS (T
A = -10 to 70° C; VA = 1.7 V - 3.3 V; Inputs: Logic 0 = GND,
Logic 1 = VL, CL = 20 pF)
16.
There must be exactly 32, 48, 64, or 128 SCLK periods per LRCK transition.
Parameters
Symbol
Min
Typ
Max
Units
Input Sample Rate
Single Speed Mode
Double Speed Mode
Fs
Fs
2
50
-
-
50
100
kHz
kHz
MCLK Pulse Width High
MCLK/LRCK = 1024
8
-
-
ns
MCLK Pulse Width Low
MCLK/LRCK = 1024
8
-
-
ns
MCLK Pulse Width High
MCLK/LRCK = 768
10
-
-
ns
MCLK Pulse Width Low
MCLK/LRCK = 768
10
-
-
ns
MCLK Pulse Width High
MCLK/LRCK = 512
15
-
-
ns
MCLK Pulse Width Low
MCLK/LRCK = 512
15
-
-
ns
MCLK Pulse Width High MCLK / LRCK = 384 or 192
25
-
-
ns
MCLK Pulse Width Low
MCLK / LRCK = 384 or 192
25
-
-
ns
MCLK Pulse Width High MCLK / LRCK = 256 or 128
35
-
-
ns
MCLK Pulse Width Low
MCLK / LRCK = 256 or 128
35
-
-
ns
Master Mode
SCLK Falling to LRCK Edge
tslrd
-20
-
20
ns
SCLK Falling to SDOUT Valid
tsdo
0
-
20
ns
SCLK Duty Cycle
40
50
60
%
Slave Mode
LRCK Duty Cycle
40
50
60
%
Rise Time of Both LRCK and SCLK
tr
-
-
10
ns
Fall Time of Both LRCK and SCLK
tf
-
-
10
ns
SCLK Period (Note 16)
Single Speed Mode
Double Speed Mode
tsclkw
tsclkw
-
-
-
-
ns
ns
SCLK Falling to LRCK Edge
tslrd
-20
-
20
ns
SCLK Falling to SDOUT Valid
Single Speed Mode
Double Speed Mode
tdss
tdss
-
-
-
-
ns
ns
1
128
()Fs
----------------------
1
64
()Fs
------------------
1
(512)Fs
1
(256)Fs



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