CS4215 datasheet(5/52 Pages) CIRRUS

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SDIN

SDOUT

t pd1

pd1

TS 1, Bit 7

TS 1, Bit 6

SCLK

pd1

pd2

TSOUT

pd2

TS 8, Bit 0

TS 1, Bit 6

FSYNC

out

TSIN

FSYNC

TS 8, Bit 0

t sckl

t sckh

sckw

SWITCHING CHARACTERISTICS (TA = 25°C; VA1, VA2, VD1, VD2 = +5V,

outputs loaded with 30 pF; Input Levels: Logic 0 = 0V, Logic 1 = VD1, VD2)

Parameter

Symbol

Min

Typ

Max

Units

SCLK period

Master Mode, XCLK = 1 (Note 8)

tsckw

-1/(Fs*bpf)

Slave Mode (XCLK = 0)

tsckw

SCLK high time

Slave Mode, XCLK = 0 (Note 9)

tsckh

SCLK low time

Slave Mode, XCLK = 0 (Note 9)

tsckl

Input Setup Time

ts1

Input Hold Time

th1

Input Transition Time

10% to 90% points

Output delay

tpd1

SCLK to TSOUT

tpd2

Output to Hi-Z state

Timeslot 8, bit 0

thz

Output to non-Hi-Z

Timeslot 1, bit 7

tnz

Input Clock Frequency

Crystals

MHz

CLKIN (Note 10)

1.024

13.5

MHz

Input Clock (CLKIN) low time

Input Clock (CLKIN) high time

Sample rate

kHz

RESET low time

(Note 11)

500

Notes:

8. In Master mode with BSEL1,0 set to 64 or 128 bits per frame (bpf), the SCLK duty cycle is 50%.

When BSEL1,0 is set to 256 bpf, SCLK will have the same duty cycle as CLKOUT.

See Internal Clock Generation section.

9. In Slave mode, FSYNC and SCLK must be derived from the master clock running the codec

(CLKIN, XTAL1, XTAL2).

10. Sample rate specifications must not be exceeded.

11. After powering up the CS4215, RESET should be held low for 50 ms to allow the voltage

reference to settle.

CS4215

DS76F2

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