CS4215 datasheet(45/52 Pages) CIRRUS

45 / 52 page

PDN and RESET

Power down, PDN, controls the PDN pin on the

codec. The line has an on-board pull-down resis-

tor thereby defining the default state as powered.

This pin only needs to be controlled if the power

down feature is used.

RESET controls the RESET pin on the codec

and is pulled up on the board. This defines the

default state as not reset. This pin only needs to

be controlled if the reset feature on the codec is

needed. Since the codec does require a reset at

power up, a power-up reset circuit is included on

the board. A reset switch is also included to reset

the device without having to remove the power

supply. The power-up reset plus switch are logi-

cally OR’ed with the RESET pin on header J14.

PIO Lines

The parallel input/output, PIO, lines are pulled

up on the evaluation board. If they are to be used

as inputs, they should be driven by open-collec-

tor gates since inadvertently setting the PIO bits

low in software will force the external lines low.

The PIO lines are available on header J14.

The PIO lines also go through a high-impedance

buffer and drive LED’s on the evaluation board.

When the LED is on, the corresponding bit is 1

or high. The LED’s provide a visual indication

that may be used to verify that the software is

writing the bits correctly.

CLOCKS

The CDB4215 can accommodate all clocking

modes supported by the CS4215. A CLKIN

BNC, as shown in Figure 5 allows the CLKIN

pin on the CS4215 to be used as the master

clock source. The two crystals listed in the

CS4215 data sheet are also provided and support

all the audio and multimedia standard sample

frequencies. The master clock is selected via a

CS4215 internal register from control mode.

The CLKOUT BNC is a buffered version of the

CLKOUT pin on the CS4215. CLKOUT is al-

ways 256 ti mes th e programmed sample

frequency in data mode. CLKOUT is held low in

control mode.

LAYOUT ISSUES

Figure 6 contains the silk screen, Figure 7 con-

tains the top-side copper layer, and Figure 8

contains the bottom-side copper layer of the

CDB4215 evaluation board. These plots are in-

cluded to provide an example of how to layout a

PCB for the codec. Two of the more important

aspects are the position of the ground plane split,

which is next to the part - NOT UNDER IT, and

the ground plane fill between traces on both lay-

ers, which minimizes coupling of radiated

energy.

U5D

74HC132

CLKIN

74HC132

U5A

R29

CS4215

R16

10 k

R32

1 k

Figure 5. CLKIN

CDB4215

DS76DB3

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