Capability

Features

Allows the reconfiguration of a single channel without affecting the

operation of other channels

Transceiver dynamic reconfigura-

tion

PCS Features

The Cyclone V core logic connects to the PCS through an 8, 10, 16, 20, 32, or 40 bit interface, depending on

the transceiver data rate and protocol. Cyclone V devices contain PCS hard IP to support PCIe Gen1 and

Gen2, Gbps Ethernet (GbE), Serial RapidIO

Most of the standard and proprietary protocols from 614 Mbps to 6.144 Gbps are supported.

Table 23: Transceiver PCS Features for Cyclone V Devices

Receiver Data Path Feature

Transmitter Data Path Feature

Data Rates(Gbps)

PCS Support

• Word aligner

• Deskew FIFO

• Rate-match FIFO

• 8B/10B decoder

• Byte deserializer

• Byte ordering

• Receiver phase compensa-

tion FIFO

• Phase compensation FIFO

• Byte serializer

• 8B/10B encoder

• Transmitter bit-slip

0.614 to 6.144

3-Gbps and 6-Gbps

Basic

• Dedicated PCIe PHY IP

core

• PIPE 2.0 interface to the

core logic

• Dedicated PCIe PHY IP core

• PIPE 2.0 interface to the core

logic

2.5 and 5.0

PCIe Gen1

(x1, x2, x4)

PCIe Gen2

( x1, x2, x4)

(10)

• Custom PHY IP core with

preset feature

• GbE receiver synchroniza-

tion state machine

• Custom PHY IP core with

preset feature

• GbE transmitter synchroniza-

tion state machine

1.25

GbE

• Dedicated XAUI PHY IP

core

• XAUI synchronization state

machine for realigning four

channels

• Dedicated XAUI PHY IP core

• XAUI synchronization state

machine for bonding four

channels

3.125

XAUI

(11)

3.75

HiGig

Cyclone V Device Overview

Altera Corporation

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PCS Features

26

2013.12.26