Member Code

Resource

D6

D5

1

1

HPS Hard Memory Controller

Dual-core

Dual-core

ARM Cortex-A9 MPCore Processor

Related Information

I/O Features in Cyclone V Devices

Provides the number of LVDS channels in each device package.

Package Plan

Table 15: Package Plan for Cyclone V ST Devices

The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific I/O

pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.

F896

(31 mm)

Member Code

XCVR

HPS I/O

FPGA GPIO

9

(9)

181

288

D5

9

(9)

181

288

D6

use only up to seven full-duplex transceiver channels for CPRI, and up to six full-duplex channels for PCIe

Gen2. The CMU channels are not considered full-duplex channels.

Cyclone V Device Overview

Altera Corporation

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CV-51001

Package Plan

16

2013.12.26