Figure 10: Device Chip Overview for Cyclone V GX and GT Devices

The figure shows a Cyclone V FPGA with transceivers. Different Cyclone V devices may have a different

floorplans than the one shown here.

I/O, LVDS, and Memory Interface

I/O, LVDS, and Memory Interface

Hard Memory Controller

Hard Memory Controller

Core Logic Fabric and MLABs

Variable-Precision DSP Blocks

M10K Internal Memory Blocks

Transceiver

PMA

Transceiver

PMA

Transceiver

PMA

Hard

PCS

Hard

PCS

Hard

PCS

Transceiver

Individual Channels

PMA Features

To prevent core and I/O noise from coupling into the transceivers, the PMA block is isolated from the rest

of the chip—ensuring optimal signal integrity. For the transceivers, you can use the channel PLL of an unused

receiver PMA as an additional transmit PLL.

Table 22: PMA Features of the Transceivers in Cyclone V Devices

Capability

Features

Driving capability up to 6.144 Gbps

Backplane support

Superior jitter tolerance

PLL-based clock recovery

Flexible deserialization width and configurable word alignment pattern

Programmable deserialization and

word alignment

• Up to 14.37 dB of pre-emphasis and up to 4.7 dB of equalization

• No decision feedback equalizer (DFE)

Equalization and pre-emphasis

614 Mbps to 6.144 Gbps

Ring oscillator transmit PLLs

20 MHz to 400 MHz

Input reference clock range

Altera Corporation

Cyclone V Device Overview

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PMA Features

CV-51001

2013.12.26