AD5686 datasheet(7/28 Pages) AD

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Data Sheet

AD5686/AD5684

Rev. A | Page 7 of 28

DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4

and Figure 5. VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.

Table 5.

1.8 V ≤ VLOGIC < 2.7 V

2.7 V ≤ VLOGIC ≤ 5.5 V

Parameter1

Symbol

Min

Max

Min

Max

Unit

SCLK Cycle Time

SCLK High Time

SCLK Low Time

SYNC to SCLK Falling Edge

Data Setup Time

Data Hold Time

SCLK Falling Edge to SYNC Rising Edge

Minimum SYNC High Time

SDO Data Valid from SCLK Rising Edge

t10

SCLK Falling Edge to SYNC Rising Edge

t11

SYNC Rising Edge to SCLK Rising Edge

t12

Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.

Circuit and Timing Diagrams

Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications

Figure 4. Daisy-Chain Timing Diagram

200µA

IOL

200µA

IOH

VOH (MIN)

TO OUTPUT

20pF

SDO

SDIN

SYNC

SCLK

DB23

DB0

DB23

DB0

DB23

INPUT WORD FOR DAC N

UNDEFINED

INPUT WORD FOR DAC N + 1

INPUT WORD FOR DAC N

DB0

t11

t12

t10

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