AD5686 datasheet(6/28 Pages) AD

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AD5686/AD5684

Data Sheet

Rev. A | Page 6 of 28

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.

VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.

Table 4.

1.8 V ≤ VLOGIC < 2.7 V

2.7 V ≤ VLOGIC ≤ 5.5 V

Parameter1

Symbol

Min

Max

Min

Max

Unit

SCLK Cycle Time

SCLK High Time

SCLK Low Time

SYNC to SCLK Falling Edge Setup Time

Data Setup Time

Data Hold Time

SCLK Falling Edge to SYNC Rising Edge

Minimum SYNC High Time

SYNC Falling Edge to SCLK Fall Ignore

LDAC Pulse Width Low

t10

SCLK Falling Edge to LDAC Rising Edge

t11

SCLK Falling Edge to LDAC Falling Edge

t12

RESET Minimum Pulse Width Low

t13

RESET Pulse Activation Time

t14

Power-Up Time2

4.5

μs

1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.

2 Time to exit power-down to normal mode of AD5686/AD5684 operation, 32nd clock edge to 90% of DAC midscale value, with output unloaded.

Figure 2. Serial Write Operation

SCLK

SYNC

SDIN

DB23

t10

t11

LDAC1

LDAC2

t12

1ASYNCHRONOUS LDAC UPDATE MODE.

2SYNCHRONOUS LDAC UPDATE MODE.

RESET

t13

t14

VOUT

DB0

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