LTC1289BCSW datasheet(19/28 Pages) LINER

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LTC1289

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Figure 14. Reference Input Equivalent Circuit

RON

8pF – 40pF

LTC1289

REF+

ROUT

VREF

EVERY 4 ACLK CYCLES

REF–

LTC1289 AIF14

pins on the package ends (DGND and CH0). Grounding

any unused inputs (especially the end pin, CH0) will also

reduce outside coupling into high source resistances.

4. Sample and Hold

Single-Ended Inputs

The LTC1289 provides a built-in sample and hold (S&H)

function for all signals acquired in the single-ended mode

(COM pin grounded). This sample and hold allows the

LTC1289 to convert rapidly varying signals (see typical

curve of S&H Acquisition Time vs Source Resistance). The

input voltage is sampled during the tSMPL time as shown

in Figure 10. The sampling interval begins after the fourth

MUX address bit is shifted in and continues during the

remainder of the data transfer. On the falling edge of the

final SCLK, the S&H goes into hold mode and the conver-

sion begins. The voltage will be held on either the 8th, 12th

or 16th falling edge of the SCLK depending on the word

length selected.

Differential Inputs

With differential inputs or when the COM pin is not tied to

ground, the A/D no longer converts just a single voltage

but rather the difference between two voltages. In these

cases, the voltage on the selected “+” input is still sampled

and held and therefore may be rapidly time varing just as

in single ended mode. However, the voltage on the se-

lected “–” input must remain constant and be free of noise

and ripple throughout the conversion time. Otherwise, the

differencing operation may not be performed accurately.

The conversion time is 52 ACLK cycles. Therefore, a

change in the “–” input voltage during this interval can

cause conversion errors. For a sinusoidal voltage on the

“–” input this error would be:

VERROR (MAX) = VPEAK × 2 × π × f(“–”) ×

Where f(“–”) is the frequency of the “–” input voltage,

VPEAK is its peak amplitude and fACLK is the frequency of

the ACLK. In most cases VERROR will not be significant. For

APPLICATI

I FOR ATIO

a 60Hz signal on the “–” input to generate a 1/4LSB error

(150

µV) with the converter running at ACLK = 2MHz, its

peak value would have to be 15mV.

5. Reference Inputs

The voltage between the reference inputs of the LTC1289

defines the voltage span of the A/D converter. The refer-

ence inputs will have transient capacitive switching cur-

rents due to the switched capacitor conversion technique

(see Figure 14). During each bit test of the conversion

(every 4 ACLK cycles), a capacitive current spike will be

generated on the reference pins by the A/D. These current

spikes settle quickly and do not cause a problem. How-

ever, if slow settling circuitry is used to drive the reference

inputs, care must be taken to insure that transients caused

by these current spikes settle completely during each bit

test of the conversion.

When driving the reference inputs, two things should be

kept in mind:

1. Transients on the reference inputs caused by the

capacitive switching currents must settle completely

during each bit test (each 4 ACLK cycles). Figures 15

and 16 show examples of both adequate and poor

settling. Using a slower ACLK will allow more time for

the reference to settle. However, even at the maximum

ACLK rate of 2MHz most references and op amps can

be made to settle within the 2

µs bit time. For example

an LT1019 used in the shunt mode with a 10

µF bypass

capacitor will settle adequately. To minimize power an

LT1004-2.5 can be used with a 10

µF bypass capacitor.

For lower value references the LT1004-1.2 with a 1

µF

bypass capacitor can be used.

fACLK

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