LTC1289BCSW datasheet(17/28 Pages) LINER

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LTC1289

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APPLICATI

I FOR ATIO

3. Analog Inputs

Because of the capacitive redistribution A/D conversion

techniques used, the analog inputs of the LTC1289 have

capacitive switching input current spikes. These current

spikes settle quickly and do not cause a problem. How-

ever, if large source resistances are used or if slow settling

op amps drive the inputs, care must be taken to insure that

the transients caused by the current spikes settle com-

pletely before the conversion begins.

Source Resistance

The analog inputs of the LTC1289 look like a 100pF

capacitor (CIN) is series with a 1500Ω resistor (RON) as

shown in Figure 9. This value for RON is for VCC = 2.7V.

With larger supply voltages RON will be reduced. For

example with VCC = 2.7V and V –= –2.7V RON becomes

500

Ω. CIN gets switched between the selected “+” and “–”

inputs once during each conversion cycle. Large external

source resistors and capacitances will slow the settling of

Figure 10. “+” and “–” Input Settling Windows

the inputs. It is important that the overall RC time con-

stants be short enough to allow the analog inputs to

completely settle within the allotted time.

“+” Input Settling

This input capacitor is switched onto the “+” input during

the sample phase (tSMPL, see Figure 10). The sample

phase starts at the 4th SCLK cycle and lasts until the falling

edge of the last SCLK (the 8th, 12th or 16th SCLK cycle

depending on the selected word length). The voltage on

the “+” input must settle completely within this sample

time. Minimizing RSOURCE+ and C1 will improve the input

settling time. If large “+” input source resistance must be

used, the sample time can be increased by using a slower

SCLK frequency or selecting a longer word length. With

the minimum possible sample time of 4

µs, RSOURCE+ < 2k

and C1 < 20pF will provide adequate settling.

“–” Input Settling

At the end of the sample phase the input capacitor switches

to the “–” input and the conversion starts (see Figure 10).

During the conversion, the “+” input voltage is effectively

“held” by the sample and hold and will not affect the

conversion result. However, it is critical that the “–” input

voltage be free of noise and settle completely during the

first four ACLK cycles of the conversion time. Minimizing

RSOURCE– and C2 will improve settling time. If large “–”

input source resistance must be used, the time allowed for

Figure 9. Analog Input Equivalent Circuit

SCLK

“+” INPUT

ACLK

1289 AIF10

234

• • •

MUX ADDRESS

SHIFTED IN

tSMPL

LAST SCLK (8TH, 12TH OR 16TH DEPENDING ON WORK LENGTH)

234

1ST BIT TEST

“–” INPUT MUST SETTLE

DURING THIS TIME

SAMPLE

HOLD

“+” INPUT

MUST SETTLE

DURING THIS TIME

“–” INPUT

• • •

4TH SCLK

RON = 1.5k

LAST SCLK

CIN =

100pF

LTC1289

“+”

INPUT

RSOURCE +

VIN +

“–”

INPUT

RSOURCE –

VIN –

LTC1289 AIF09

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