AT6002-2AC datasheet(19/28 Pages) ATMEL

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AT6000(LV) Series

AC Timing Characteristics – 5V Operation

Notes:

1. TTL buffer delays are measured from a V

IH of 1.5V at the pad to the internal VIH at A. The input buffer load is constant.

2. CMOS buffer delays are measured from a VIH of 1/2 VCC at the apd to the internal VIH at A. The input buffer load is constant.

3. Buffer delay is to a pad voltage of 1.5V with one output switching.

4. Max specifications are the average of mas t

PDLH and tPDHL.

5. Parameter based on characterization and simulation; not tested in production

6. Exact power calculation is available in an Atmel application note.

7. Load Definition: 1 = Load of one A or B input; 2 = Load of one L input; 3 = Constant Load; 4 = Tester Load of 50 pF.

Delays are based on fixed load. Loads for each type of device are described in the notes. Delays are in nanoseconds.

Worst case: V

CC = 4.75V to 5.25V. Temperature = 0°C to 70°C.

Cell Function

Parameter

From

Load

Definition

(7)

-1

-2

-4

Units

Wire

(4)

PD (max)

(4)

A, B, L

A, B

0.8

1.2

1.8

NAND

PD (max)

A, B, L

1.6

2.2

3.2

XOR

tPD (max)

A, B, L

1.8

2.4

4.0

AND

PD (max)

A, B, L

1.7

2.2

3.2

MUX

tPD (max)

A, B

1.7

2.3

4.0

2.1

3.0

4.9

D-Flip-flop

(5)

setup (min)

A, B, L

CLK

1.5

2.0

3.0

D-Flip-flop

(5)

hold (min)

CLK

A, B, L

000

D-Flip-flop

tPD (max)

CLK

1.5

2.0

3.0

Bus Driver

PD (max)

2.0

2.6

4.0

Repeater

tPD (max)

L, E

1.3

1.6

2.3

L, E

1.7

2.1

3.0

Column Clock

PD (max)

GCLK, A, ES

CLK

1.8

2.4

3.0

Column Reset

PD (max)

GRES, A, EN

RES

1.8

2.4

3.0

Clock Buffer

(5)

tPD (max)

CLOCK PIN

GCLK

1.6

2.0

2.9

Reset Buffer

(5)

PD (max)

RESET PIN

GRES

1.5

1.9

2.8

TTL Input

(1)

PD (max)

I/O

1.0

1.2

1.5

CMOS Input

(2)

tPD (max)

I/O

1.3

1.4

2.3

Fast Output

(3)

PD (max)

I/O PIN

3.3

3.5

6.0

Slow Output

(3)

PD (max)

I/O PIN

7.5

8.0

12.0

Output Disable

(5)

tPXZ (max)

I/O PIN

3.1

3.3

5.5

Fast Enable

(3)(5)

PXZ (max)

I/O PIN

3.8

4.0

6.5

Slow Enable

(3)(5)

PXZ (max)

I/O PIN

8.2

8.5

12.5

Device

Cell Types

Outputs

ICC (max)

Cell

(6)

Wire, XWire, Half-adder, Flip-flop

A, B

4.5 µA/MHz

Bus

(6)

Wire, XWire, Half-adder, Flip-flop, Repeater

2.5 µA/MHz

Column Clock

(6)

Column Clock Driver

CLK

40 µA/MHz

= Preliminary Information

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