1

Features

– System Speeds > 100 MHz

– Flip-flop Toggle Rates > 250 MHz

– 1.2 ns/1.5 ns Input Delay

– 3.0 ns/6.0 ns Output Delay

– Complete/Partial In-System Reconfiguration

– No Loss of Data or Machine State

– Adaptive Hardware

– 3.3 (V

– Reusable Custom Hard Macro Functions

– Standby Current of 500 µA/ 200 µA

– Typical Operating Current of 15 to 170 mA

– Independently Controlled Column Clocks

– Independently Controlled Column Resets

– Clock Skew Less Than 1 ns Across Chip

– TTL/CMOS Input Thresholds

– Open Collector/Tristate Outputs

– Programmable Slew-rate Control

– I/O Drive of 16 mA (combinable to 64 mA)

Description

AT6000 Series SRAM-based Field Programmable Gate Arrays (FPGAs) are ideal for

use as reconfigurable coprocessors and implementing compute-intensive logic.

Supporting system speeds greater than 100 MHz and using a typical operating current

of 15 to 170 mA, AT6000 Series devices are ideal for high-speed, compute-intensive

user with the ability to implement adaptive hardware and perform hardware

acceleration.

The patented AT6000 Series architecture employs a symmetrical grid of small yet

powerful cells connected to a flexible busing network. Independently controlled clocks

and resets govern every column of cells. The array is surrounded by programmable

I/O.

AT6000 Series Field Programmable Gate Arrays

Device

AT6002

AT6003

AT6005

AT6010

Usable Gates

6,000

9,000

15,000

30,000

Cells

1,024

1,600

3,136

6,400

Registers (maximum)

1,024

1,600

3,136

6,400

I/O (maximum)

96

120

108

204

Typ. Operating Current (mA)

15 - 30

25 - 45

40 - 80

85 - 170

Cell Rows x Columns

32 x 32

40 x 40

56 x 56

80 x 80

Rev. 0264F–10/99

Coprocessor

Field

Programmable

Gate Arrays

AT6000(LV)

Series

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