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TCS3772 датащи(PDF) 26 Page - ams AG |
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TCS3772 датащи(HTML) 26 Page - ams AG |
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26 / 33 page ![]() TCS3772 COLOR LIGHT-TO-DIGITAL CONVERTER with PROXIMITY SENSING TAOS145B − SEPTEMBER 2012 25 The LUMENOLOGY r Company r r Copyright E 2012, TAOS Inc. www.taosinc.com Status Register (0x13) The Status Register provides the internal status of the device. This register is read only. Table 16. Status Register 6 75 4 AVALID 2 31 0 STATUS Reserved Resv AINT Reset 0x00 Reserved PINT PVALID FIELD BIT DESCRIPTION Reserved 7:6 Reserved. PINT 5 Proximity Interrupt. AINT 4 Clear channel Interrupt. Reserved 3:2 Reserved. PVALID 1 Proximity Valid. Indicates that a proximity cycle has completed since PEN was asserted. AVALID 0 RGBC Valid. Indicates that the RGBC cycle has completed since AEN was asserted. RGBC Channel Data Registers (0x14 − 0x1B) Clear, red, green, and blue data is stored as 16-bit values. To ensure the data is read correctly, a two-byte read I2C transaction should be used with a read word protocol bit set in the command register. With this operation, when the lower byte register is read, the upper eight bits are stored into a shadow register, which is read by a subsequent read to the upper byte. The upper register will read the correct value even if additional ADC integration cycles end between the reading of the lower and upper registers. Table 17. ADC Channel Data Registers REGISTER ADDRESS BITS DESCRIPTION CDATA 0x14 7:0 Clear data low byte CDATAH 0x15 7:0 Clear data high byte RDATA 0x16 7:0 Red data low byte RDATAH 0x17 7:0 Red data high byte GDATA 0x18 7:0 Green data low byte GDATAH 0x19 7:0 Green data high byte BDATA 0x1A 7:0 Blue data low byte BDATAH 0x1B 7:0 Blue data high byte Proximity Data Registers (0x1C − 0x1D) Proximity data is stored as a 16-bit value. To ensure the data is read correctly, a two-byte read I2C transaction should be used with a read word protocol bit set in the command register. With this operation, when the lower byte register is read, the upper eight bits are stored into a shadow register, which is read by a subsequent read to the upper byte. The upper register will read the correct value even if additional ADC integration cycles end between the reading of the lower and upper registers. Table 18. PDATA Registers REGISTER ADDRESS BITS DESCRIPTION PDATA 0x1C 7:0 Proximity data low byte PDATAH 0x1D 7:0 Proximity data high byte |
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