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Revision 2.3

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AS8525

Datasheet - Application In form atio n

8.9.1 Register Definitions

A total of 32 registers, each of 8-bits which include configuration, diagnostic, and backup are available. The registers can be accessed using the

2-wire or the 4-wire serial interface. Table 21 provides a description of all registers.

Table 21. Registers

Addr

Register Name Default Value

RD/WR

Description

Configuration and Control Registers

0x00

Reserved

0x01

Reserved

0 x 02

Reserved

0 x 03

Device

Configuration

Register

On POR_VCC

0000_1100

RD/WR

D0 Reserved

D1 Reserved

D2 Enable/Disable Over-Temperature Monitor. (0-Disabled, 1-Enabled)

D3 Enable/Disable LIN Transceiver. (0-Disabled, 1-Enabled)

D4- D7 Reserved

0 x 04

Device Control

Register

On POR_VSUP

0000_0001

RD/WR

D0 High Slew / Low Slew control.

1 High Slew mode

0 Low Slew Mode

D1- D7 Reserved

0 x 05

Temporary

Shutdown

Register

On POR_VCC

0000_0000

RD/WR

D0 Temporary shutdown control bit

1 Enter temporary shutdown

D1- D7 Reserved

0 x 06

Window Watch

Dog Trigger

Register

On POR_VCC

0000_0000

WR

D0 Window Watchdog Trigger

D1 Timeout Watchdog trigger bit

Upon a trigger, the bit will be cleared within 2 internal clock cycles.

D2- D7 Reserved

0 x 07

Reserved

0x0A

Signal Path

Control Register

On POR_VCC

0000_0000

RD/WR

D0 Reserved

D1 Enable/Disable current channel chopper (0 Disabled, 1 Enabled)

D2 Reserved

D3 Reserved

D4 Enable/Disable voltage attenuator (0 Disabled, 1 Enabled)

D5 Enable/Disable PGA (0 Disabled, 1 Enabled)

D6-D7 PGA gain selection

10 00 Gain-5, 01 Gain-25, 10 Gain-50, 11 Gain-100

0x0B

Reserved

0x0C

Reserved

0x0D

Reserved

0x0E

Watchdog Timer

Control Register

On POR_VCC

0000_0000

RD/WR

D0 Timer resolution

0 1 second, 1 32 seconds

D1-D7 Timeout period

If D0=1, then timeout period = D[7:1]*64*0.512 seconds, else timeout period =

D[7:1]*0.512 seconds

0x0F

Reserved

Backup Registers