AS8506 datasheet(45/89 Pages) AMSCO

45 / 89 page

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 45

Devic e I n te r f ac e

In the address allocation process, the

CVT_NOK_IN/CVT_NOK_OUT pins of AS8506 are used. After

the successful SPI3 address allocation write operation, all

AS8506 devices including Master will store the top device

address (sent by Master in SPI3 address allocation write) as its

address. The top device identifies itself as top most device and

registers the address as its final address and at first rising edge

of clock all devices force ‘High’ on its CVT_NOK_OUT pin. The

concept of address allocation is: after the STOP of SPI3, at every

falling edge of the clock each device will sample its

CVT_NOK_IN pin. If CVT_NOK_IN pin is ‘High’, the device will

decrement the assigned address by ‘1’ and continue to force

‘High’ on its CVT_NOK_OUT pin at rising edge of clock. If

CVT_NOK_IN is sampled to be ‘Low’, then the address value at

forcing ‘High’ on its CVT_NOK_OUT pin and makes it ‘Low’ at

next rising edge of clock.

In Figure 38, top most device pins are suffixed with ‘6’ down to

lower most device (Master) pins suffixed with ‘1’ in descending

order. There is no device above topmost device, CVT_NOK_IN6

is always ‘Low’; therefore the address sent by Master is final

address for the top device. For the fifth device the

CVT_NOK_IN5 is ‘Low’ for one clock cycle, the address is

decremented once. For the fourth device CVT_NOK_IN4 is ‘Low’

for two clock cycles, the address is decremented twice before

registering it as final address. This procedure is continued and

finally the Master device CVT_ONK_IN1 is ‘Low’ for 5 clock

cycles, the address is decremented five times and finally

address register will have value of “000001” as its final address.

The microcontroller can identify the end of address allocation

procedure in two ways:

• One way is by probing CVT_NOK_OUT of Master after

initiating address allocation process for a pulse.

• The other method is by polling bit0 of spi3_cmd_reg

During SPI3 address allocation write operation, if a CRC error

occurs in the any of the Slaves, the Master indicates this failure

of SPI3 transaction to all Slaves by driving TST bit ‘High’. All

Slaves should terminate the address allocation process if a

‘High’ TST bit is seen during start address allocation process

SPI3 write operation. The Master will indicate the failure of

address allocation process to μC by asserting a flag in the

spi3_sts_reg register and sending interrupt pulse on its

CVT_NOK_OUT pin.

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