AS8506 datasheet(36/89 Pages) AMSCO

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AS8506 – 36

ams Datasheet, Confidential:2013-Sep [1-00]

De tail ed De sc rip t ion

Initialization Sequence

The power-up initialization sequence diagram for AS8506 is

shown in Figure 29.

• When the power supply is switched ON, initially VSUP POR

output Vsup_por_n is ‘Low’; hence all the digital logic will

be in reset state.

• Once the VSUP crosses the Vsup_por_th, the VSUP POR

output becomes ‘High’ enabling the oscillator and

high-precision bandgap (HPBG) block.

• The digital block is now operational. It will now enable the

V5V LDO and waits for V5V_por_n high signal from the

V5V POR block.

• Once the V5V crosses V5V_por_th, the V5V_por_n will be

‘High’. The OTP auto load command is generated by ‘High’

on otp_por_n signal. Now the device waits for Tauto_load

period for OTP contents to load into digital local registers.

• After the OTP contents are loaded into digital local

registers, the device power-up sequence is completed.

The device enters into SLEEP mode. In SLEEP mode, the

LDO, oscillator and HPBG are disabled.

• The wake-up circuit monitors the WAKE_IN pin for

wake-up pulse. When a wake-up pulse is received, the

oscillator and HPBG block are enabled and device enters

into WAKE mode. In the WAKE mode, the device enables

V5V LDO and waits for V5V_por_n high signal.

• Once the V5V crosses V5V_por_th, the V5V_por_n will be

‘High’ and the device enters into WAIT mode. In WAIT

mode the device waits for trigger pulse on TRIG_IN pin

from microcontroller. In this state, if a short or long pulse

trigger signal is received on TRIG_IN within Twmode_tout

period, the AS8506 enters into NORMAL mode and

performs required operations based on trigger pulse.

AS8506 датащи(PDF) 36 Page - ams AG