MSC1202Y2RHHT datasheet(82/92 Pages) TI

82 / 92 page

MSC1200

MSC1201

MSC1202

SBAS317E − APRIL 2004 − REVISED MAY 2006

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Milliseconds TImer Interrupt (MSINT)

Reset Value

SFR FAh

WRT

MSINT6

MSINT5

MSINT4

MSINT3

MSINT2

MSINT1

MSINT0

7Fh

The clock used for this timer is the 1ms clock, which results from dividing the system clock by the values in registers

MSECH:MSECL. Reading this register is necessary for clearing the interrupt; however, AI in EICON (SFR D8h) must also

be cleared.

WRT

Write Control. Determines whether to write the value immediately or wait until the current count is finished.

bit 7

Read = 0.

0 = Delay Write Operation. The MSINT value is loaded when the current count expires.

1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation.

MSINT6−0

Milliseconds Count. Normal operation would use 1ms as the clock interval.

bits 6−0

MS Interrupt Interval = (1 + MSINT)

• (MSEC + 1) • tCLK

One Microsecond Timer (USEC)

Reset Value

SFR FBh

FREQ5

FREQ4

FREQ3

FREQ2

FREQ1

FREQ0

03h

FREQ5−0

Clock Frequency − 1. This value + 1 divides the system clock to create a 1

µs Clock.

bits 5−0

USEC = CLK/(FREQ + 1). This clock is used to set Flash write time. See FTCON (SFR EFh).

One Millisecond TImer Low Byte (MSECL)

Reset Value

SFR FCh

MSECL7

MSECL6

MSECL5

MSECL4

MSECL3

MSECL2

MSECL1

MSECL0

9Fh

MSECL7−0 One Millisecond Timer Low Byte. This value in combination with the next register is used to create a 1ms clock.

bits 7−0

1ms = (MSECH

• 256 + MSECL + 1) • tCLK. This clock is used to set Flash erase time. See FTCON (SFR EFh).

One Millisecond Timer High Byte (MSECH)

Reset Value

SFR FDh

MSECH7

MSECH6

MSECH5

MSECH4

MSECH3

MSECH2

MSECH1

MSECH0

0Fh

MSECH7−0 One Millisecond Timer High Byte. This value in combination with the previous register is used to create a 1ms clock.

bits 7−0

1ms = (MSECH

• 256 + MSECL + 1) • tCLK.

One Hundred Millisecond Timer (HMSEC)

Reset Value

SFR FEh

HMSEC7

HMSEC6

HMSEC5

HMSEC4

HMSEC3

HMSEC2

HMSEC1

HMSEC0

63h

WRT

Write Control. Determines whether to write the value immediately or wait until the current count is finished.

Read = 0.

HMSEC7−0 One Hundred Millisecond Timer. This clock divides the 1ms clock to create a 100ms clock.

bits 7−0

100ms = (MSECH

• 256 + MSECL + 1) • (HMSEC + 1) • tCLK.

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