64GA106 datasheet(202/330 Pages) MICROCHIP

202 / 330 page

PIC24FJ256GA110 FAMILY

DS39905E-page 202

 2010 Microchip Technology Inc.

PMCON: PARALLEL MASTER PORT CONTROL REGISTER

R/W-0

U-0

R/W-0

PMPEN

—

PSIDL

ADRMUX1

ADRMUX0

PTBEEN

PTWREN

PTRDEN

bit 15

bit 8

R/W-0

R/W-0(1)

R/W-0

CSF1

CSF0

ALP

CS2P

CS1P

BEP

WRSP

RDSP

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

PMPEN:

Parallel Master Port Enable bit

= PMP enabled

= PMP disabled, no off-chip access performed

bit 14

Unimplemented:

Read as ‘0’

bit 13

PSIDL:

Stop in Idle Mode bit

= Discontinue module operation when device enters Idle mode

= Continue module operation in Idle mode

bit 12-11

ADRMUX<1:0>:

Address/Data Multiplexing Selection bits

= Reserved

= All 16 bits of address are multiplexed on PMD<7:0> pins

= Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 3 bits are multiplexed on

PMA<10:8>

= Address and data appear on separate pins

bit 10

PTBEEN:

Byte Enable Port Enable bit (16-Bit Master mode)

= PMBE port enabled

= PMBE port disabled

bit 9

PTWREN:

Write Enable Strobe Port Enable bit

= PMWR/PMENB port enabled

= PMWR/PMENB port disabled

bit 8

PTRDEN:

Read/Write Strobe Port Enable bit

= PMRD/PMWR port enabled

= PMRD/PMWR port disabled

bit 7-6

CSF<1:0>:

Chip Select Function bits

= Reserved

= PMCS1 and PMCS2 function as chip select

= PMCS2 functions as chip select, PMCS1 functions as address bit 14

= PMCS1 and PMCS2 function as address bits 15 and 14

bit 5

ALP:

Address Latch Polarity bit(1)

= Active-high (PMALL and PMALH)

= Active-low (PMALL and PMALH)

bit 4

CS2P:

Chip Select 2 Polarity bit(1)

= Active-high (PMCS2/PMCS2)

=Active-low (PMCS2/PMCS2)

bit 3

CS1P:

Chip Select 1 Polarity bit(1)

= Active-high (PMCS1/PMCS1)

=Active-low (PMCS1/PMCS1)

Note 1:

These bits have no effect when their corresponding pins are used as address lines.

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