64GA106 datasheet(201/330 Pages) MICROCHIP

201 / 330 page

 2010 Microchip Technology Inc.

DS39905E-page 201

PIC24FJ256GA110 FAMILY

18.0

PARALLEL MASTER PORT

(PMP)

The Parallel Master Port (PMP) module is a parallel,

8-bit I/O module, specifically designed to communicate

with a wide variety of parallel devices, such as commu-

nication peripherals, LCDs, external memory devices

and microcontrollers. Because the interface to parallel

peripherals varies significantly, the PMP is highly

configurable.

Key features of the PMP module include:

• Up to 16 Programmable Address Lines

• Up to 2 Chip Select Lines

• Programmable Strobe Options:

- Individual Read and Write Strobes or;

- Read/Write Strobe with Enable Strobe

• Address Auto-Increment/Auto-Decrement

• Programmable Address/Data Multiplexing

• Programmable Polarity on Control Signals

• Legacy Parallel Slave Port Support

• Enhanced Parallel Slave Support:

- Address Support

- 4-Byte Deep Auto-Incrementing Buffer

• Programmable Wait States

• Selectable Input Voltage Levels

FIGURE 18-1:

PMP MODULE OVERVIEW

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F

Family

Reference

Manual”

Section 13. “Parallel Master Port (PMP)”

(DS39713).

PMA<0>

PMBE

PMRD

PMWR

PMD<7:0>

PMENB

PMRD/PMWR

PMCS1

PMA<1>

PMA<13:2>

PMALL

PMALH

PMA<7:0>

PMA<15:8>

EEPROM

Address Bus

Data Bus

Control Lines

PIC24F

LCD

FIFO

Microcontroller

8-Bit Data

Up to 16-Bit Address

Parallel Master Port

Buffer

PMA<14>

PMCS2

PMA<15>

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