64GA106 datasheet(204/330 Pages) MICROCHIP

204 / 330 page

PIC24FJ256GA110 FAMILY

DS39905E-page 204

 2010 Microchip Technology Inc.

PMMODE: PARALLEL MASTER PORT MODE REGISTER

R-0

R/W-0

BUSY

IRQM1

IRQM0

INCM1

INCM0

MODE16

MODE1

MODE0

bit 15

bit 8

R/W-0

WAITB1(1)

WAITB0(1)

WAITM3

WAITM2

WAITM1

WAITM0

WAITE1(1)

WAITE0(1)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

BUSY:

Busy bit (Master mode only)

= Port is busy (not useful when the processor stall is active)

= Port is not busy

bit 14-13

IRQM<1:0>:

Interrupt Request Mode bits

= Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode),

or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only)

= No interrupt generated, processor stall activated

= Interrupt generated at the end of the read/write cycle

= No interrupt generated

bit 12-11

INCM<1:0>:

Increment Mode bits

= PSP read and write buffers auto-increment (Legacy PSP mode only)

= Decrement ADDR<10:0> by 1 every read/write cycle

= Increment ADDR<10:0> by 1 every read/write cycle

= No increment or decrement of address

bit 10

MODE16:

8/16-Bit Mode bit

= 16-bit mode: Data register is 16 bits; a read or write to the Data register invokes two 8-bit transfers

= 8-bit mode: Data register is 8 bits; a read or write to the Data register invokes one 8-bit transfer

bit 9-8

MODE<1:0>:

Parallel Port Mode Select bits

= Master Mode 1 (PMCS1, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)

= Master Mode 2 (PMCS1, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)

= Enhanced PSP, control signals (PMRD, PMWR, PMCS1, PMD<7:0> and PMA<1:0>)

= Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1 and PMD<7:0>)

bit 7-6

WAITB<1:0>:

Data Setup to Read/Write Wait State Configuration bits(1)

= Data wait of 4 TCY; multiplexed address phase of 4 TCY

= Data wait of 3 TCY; multiplexed address phase of 3 TCY

= Data wait of 2 TCY; multiplexed address phase of 2 TCY

= Data wait of 1 TCY; multiplexed address phase of 1 TCY

bit 5-2

WAITM<3:0>:

Read to Byte Enable Strobe Wait State Configuration bits

1111

= Wait of additional 15 TCY

...

0001

= Wait of additional 1 TCY

0000

= No additional wait cycles (operation forced into one TCY)(2)

bit 1-0

WAITE<1:0>:

Data Hold After Strobe Wait State Configuration bits(1)

= Wait of 4 TCY

= Wait of 3 TCY

= Wait of 2 TCY

= Wait of 1 TCY

Note 1:

WAITB and WAITE bits are ignored whenever WAITM<3:0> = 0000.

A single cycle delay is required between consecutive read and/or write operations.

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