64GA106 datasheet(189/330 Pages) MICROCHIP

189 / 330 page

 2010 Microchip Technology Inc.

DS39905E-page 189

PIC24FJ256GA110 FAMILY

bit 5

ACKDT:

Acknowledge Data bit (When operating as I2C master. Applicable during master receive.)

Value that will be transmitted when the software initiates an Acknowledge sequence.

= Sends NACK during Acknowledge

= Sends ACK during Acknowledge

bit 4

ACKEN:

Acknowledge Sequence Enable bit (When operating as I2C master. Applicable during master

receive.)

= Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit. Hardware

clear at end of master Acknowledge sequence.

= Acknowledge sequence not in progress

bit 3

RCEN:

Receive Enable bit (when operating as I2C master)

= Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.

= Receives sequence not in progress

bit 2

PEN:

Stop Condition Enable bit (when operating as I2C master)

= Initiates Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.

= Stop condition not in progress

bit 1

RSEN:

Repeated Start Condition Enabled bit (when operating as I2C master)

= Initiates Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master

Repeated Start sequence.

= Repeated Start condition not in progress

bit 0

SEN:

Start Condition Enabled bit (when operating as I2C master)

= Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.

= Start condition not in progress

I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)

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