64GA106 datasheet(190/330 Pages) MICROCHIP

190 / 330 page

PIC24FJ256GA110 FAMILY

DS39905E-page 190

 2010 Microchip Technology Inc.

I2CxSTAT: I2Cx STATUS REGISTER

R-0, HSC

U-0

R/C-0, HS

R-0, HSC

ACKSTAT

TRSTAT

—

BCL

GCSTAT

ADD10

bit 15

bit 8

R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC

R-0, HSC

IWCOL

I2COV

D/A

R/W

RBF

TBF

bit 7

bit 0

Legend:

C = Clearable bit

HS = Hardware Settable bit

HSC = Hardware Settable/Clearable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

ACKSTAT:

Acknowledge Status bit

= NACK was detected last

= ACK was detected last

Hardware set or clear at end of Acknowledge.

bit 14

TRSTAT:

Transmit Status bit

(When operating as I2C master. Applicable to master transmit operation.)

= Master transmit is in progress (8 bits + ACK)

= Master transmit is not in progress

Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.

bit 13-11

Unimplemented:

Read as ‘0’

bit 10

BCL:

Master Bus Collision Detect bit

= A bus collision has been detected during a master operation

= No collision

Hardware set at detection of bus collision.

bit 9

GCSTAT:

General Call Status bit

= General call address was received

= General call address was not received

Hardware set when address matches general call address. Hardware clear at Stop detection.

bit 8

ADD10:

10-Bit Address Status bit

= 10-bit address was matched

= 10-bit address was not matched

Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.

bit 7

IWCOL:

Write Collision Detect bit

= An attempt to write to the I2CxTRN register failed because the I2C module is busy

= No collision

Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).

bit 6

I2COV:

Receive Overflow Flag bit

= A byte was received while the I2CxRCV register is still holding the previous byte

= No overflow

Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).

bit 5

D/A:

Data/Address bit (when operating as I2C slave)

= Indicates that the last byte received was data

= Indicates that the last byte received was device address

Hardware clear at device address match. Hardware set after a transmission finishes or by reception of the

slave byte.

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