64GA106 datasheet(187/330 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS39905E-page 187

PIC24FJ256GA110 FAMILY

16.3

Setting Baud Rate When

Operating as a Bus Master

To compute the Baud Rate Generator reload value, use

Equation 16-1.

EQUATION 16-1:

COMPUTING BAUD RATE

RELOAD VALUE(1,2)

16.4

Slave Address Masking

The I2CxMSK register (Register 16-3) designates

address bit positions as “don’t care” for both 7-Bit and

10-Bit Addressing modes. Setting a particular bit loca-

tion (= 1) in the I2CxMSK register causes the slave

module to respond whether the corresponding address

bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK

is set to ‘00010000’, the slave module will detect both

addresses: ‘0000000’ and ‘0010000’.

To enable address masking, the IPMI (Intelligent

Peripheral Management Interface) must be disabled by

clearing the IPMIEN bit (I2CxCON<11>).

TABLE 16-1:

I2C™ CLOCK RATES(1,2)

TABLE 16-2:

I2C™ RESERVED ADDRESSES(1)

I2CxBRG

FCY

FSCL

------------

FCY

10 000 000



------------------------------

–





–

FSCL

FCY

I2CxBRG

FCY

10 000 000



------------------------------

----------------------------------------------------------------------

Note 1:

Based on FCY = FOSC/2, Doze mode and PLL

are disabled.

These clock rate values are for guidance only.

The actual clock rate can be affected by various

system level parameters. The actual clock rate

should be measured in its intended application.

Note:

As a result of changes in the I2C™ proto-

col, the addresses in Table 16-2 are

reserved and will not be Acknowledged in

Slave mode. This includes any address

mask settings that include any of these

addresses.

Required System

FSCL

FCY

I2CxBRG Value

Actual

FSCL

(Decimal)

(Hexadecimal)

100 kHz

16 MHz

157

100 kHz

8 MHz

100 kHz

4 MHz

99 kHz

400 kHz

16 MHz

404 kHz

400 kHz

8 MHz

404 kHz

400kHz

4MHz

385kHz

400kHz

2MHz

385kHz

1 MHz

16 MHz

1.026 MHz

1MHz

8MHz

1.026MHz

1MHz

4MHz

0.909MHz

Note 1:

Based on FCY = FOSC/2, Doze mode and PLL are disabled.

These clock rate values are for guidance only. The actual clock rate can be affected by various system

level parameters. The actual clock rate should be measured in its intended application.

Slave Address

R/W Bit

Description

0000 000

General Call Address(2)

0000 000

Start Byte

0000 001

Cbus Address

0000 010

Reserved

0000 011

Reserved

0000 1xx

HS Mode Master Code

1111 1xx

Reserved

1111 0xx

10-Bit Slave Upper Byte(3)

Note 1:

The address bits listed here will never cause an address match, independent of address mask settings.

The address will be Acknowledged only if GCEN = 1.

Match on this address can only occur on the upper byte in 10-Bit Addressing mode.

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