64GA106 datasheet(185/330 Pages) MICROCHIP

185 / 330 page

 2010 Microchip Technology Inc.

DS39905E-page 185

PIC24FJ256GA110 FAMILY

16.0

INTER-INTEGRATED CIRCUIT

(I2C™)

The Inter-Integrated Circuit (I2C) module is a serial inter-

face useful for communicating with other peripheral or

microcontroller devices. These peripheral devices may

be serial EEPROMs, display drivers, A/D Converters,

etc.

The I2C module supports these features:

• Independent master and slave logic

• 7-bit and 10-bit device addresses

• General call address, as defined in the I2C protocol

• Clock stretching to provide delays for the

processor to respond to a slave data request

• Both 100 kHz and 400 kHz bus specifications.

• Configurable address masking

• Multi-Master modes to prevent loss of messages

in arbitration

• Bus Repeater mode, allowing the acceptance of

all messages as a slave regardless of the address

• Automatic SCL

A block diagram of the module is shown in Figure 16-1.

16.1

Peripheral Remapping Options

The I2C modules are tied to fixed pin assignments and

cannot be reassigned to alternate pins using Peripheral

Pin Select. To allow some flexibility with peripheral

multiplexing, the I2C2 module in 100-pin devices can

be reassigned to the alternate pins designated as

ASCL2 and ASDA2 during device configuration.

Pin assignment is controlled by the I2C2SEL Configu-

ration bit; programming this bit (= 0) multiplexes the

module to the ASCL2 and ASDA2 pins.

16.2

Communicating as a Master in a

Single Master Environment

The details of sending a message in Master mode

depends on the communications protocol for the device

being communicated with. Typically, the sequence of

events is as follows:

Assert a Start condition on SDAx and SCLx.

Send the I2C device address byte to the slave

with a write indication.

Wait for and verify an Acknowledge from the

slave.

Send the first data byte (sometimes known as

the command) to the slave.

Wait for and verify an Acknowledge from the

slave.

Send the serial memory address low byte to the

slave.

Repeat Steps 4 and 5 until all data bytes are

sent.

Assert a Repeated Start condition on SDAx and

SCLx.

Send the device address byte to the slave with

a read indication.

10. Wait for and verify an Acknowledge from the

slave.

11. Enable master reception to receive serial

memory data.

12. Generate an ACK or NACK condition at the end

of a received byte of data.

13. Generate a Stop condition on SDAx and SCLx.

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F

Family

Reference

Manual”

Section 24. “Inter-Integrated Circuit

(I2C™)”

(DS39702).

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