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64GA106 датащи(PDF) 182 Page - Microchip Technology |
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64GA106 датащи(HTML) 182 Page - Microchip Technology |
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182 / 330 page ![]() PIC24FJ256GA110 FAMILY DS39905E-page 182 2010 Microchip Technology Inc. FIGURE 15-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE) FIGURE 15-4: SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES) Serial Receive Buffer (SPIxRXB) Shift Register (SPIxSR) LSb MSb SDIx SDOx PROCESSOR 2 (SPI Slave) SCKx SSx(1) Serial Transmit Buffer (SPIxTXB) Serial Receive Buffer (SPIxRXB) Shift Register (SPIxSR) MSb LSb SDOx SDIx PROCESSOR 1 (SPI Master) Serial Clock SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0 Note 1: Using the SSx pin in Slave mode of operation is optional. 2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF. SCKx Serial Transmit Buffer (SPIxTXB) MSTEN (SPIxCON1<5>) = 1) SPIx Buffer (SPIxBUF)(2) SPIx Buffer (SPIxBUF)(2) Shift Register (SPIxSR) LSb MSb SDIx SDOx PROCESSOR 2 (SPI Enhanced Buffer Slave) SCKx SSx(1) Shift Register (SPIxSR) MSb LSb SDOx SDIx PROCESSOR 1 (SPI Enhanced Buffer Master) Serial Clock SSEN (SPIxCON1<7>) = 1, Note 1: Using the SSx pin in Slave mode of operation is optional. 2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF. SSx SCKx 8-Level FIFO Buffer MSTEN (SPIxCON1<5>) = 1 and SPIx Buffer (SPIxBUF)(2) 8-Level FIFO Buffer SPIx Buffer (SPIxBUF)(2) SPIBEN (SPIxCON2<0>) = 1 MSTEN (SPIxCON1<5>) = 0 and SPIBEN (SPIxCON2<0>) = 1 |
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