64GA106 datasheet(180/330 Pages) MICROCHIP

180 / 330 page

PIC24FJ256GA110 FAMILY

DS39905E-page 180

 2010 Microchip Technology Inc.

SPIXCON1: SPIx CONTROL REGISTER 1

U-0

R/W-0

—

DISSCK(1)

DISSDO(2)

MODE16

SMP

CKE(3)

bit 15

bit 8

R/W-0

SSEN(4)

CKP

MSTEN

SPRE2

SPRE1

SPRE0

PPRE1

PPRE0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-13

Unimplemented:

Read as ‘0’

bit 12

DISSCK:

Disable SCKx pin bit (SPI Master modes only)(1)

= Internal SPI clock is disabled; pin functions as I/O

= Internal SPI clock is enabled

bit 11

DISSDO:

Disable SDOx pin bit(2)

= SDOx pin is not used by module; pin functions as I/O

= SDOx pin is controlled by the module

bit 10

MODE16:

Word/Byte Communication Select bit

= Communication is word-wide (16 bits)

= Communication is byte-wide (8 bits)

bit 9

SMP:

SPIx Data Input Sample Phase bit

Master mode:

= Input data sampled at end of data output time

= Input data sampled at middle of data output time

Slave mode:

SMP must be cleared when SPIx is used in Slave mode.

bit 8

CKE:

SPIx Clock Edge Select bit(3)

= Serial output data changes on transition from active clock state to Idle clock state (see bit 6)

= Serial output data changes on transition from Idle clock state to active clock state (see bit 6)

bit 7

SSEN:

Slave Select Enable (Slave mode) bit(4)

=SSx pin used for Slave mode

=SSx pin not used by module; pin controlled by port function

bit 6

CKP:

Clock Polarity Select bit

= Idle state for clock is a high level; active state is a low level

= Idle state for clock is a low level; active state is a high level

bit 5

MSTEN:

Master Mode Enable bit

= Master mode

=Slave mode

Note 1:

If DISSCK = 0, SCKx must be configured to an available RPn pin (or to ASCK1 for SPI1). See

Section 10.4 “Peripheral Pin Select”

for more information.

If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin

Select”

for more information.

The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed

SPI modes (FRMEN = 1).

If SSEN = 1, SSx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select”

for more information.

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